AR# 60838


Vivado IP Integrator, Block Memory Generator - "[BD 41-237] Bus Interface property MASTER_TYPE does not match between /axi_bram_ctrl_0_bram/BRAM_PORTA(BRAM_CTRL) and /BRAM_PORTA(OTHER)"?


When trying to create a HDL wrapper for a block diagram, I receive the following critical warnings:


What can cause this issue?


This warning is related to mode settings in the Block Memory Generator (BMG) GUI.

When using the memory with an AXI BRAM Controller, the Mode option of the BMG GUI must be set to "BRAM Controller" to allow the AXI BRAM Controller to parameterize the core.

For all other uses, select Stand Alone mode, and ensure that all settings are compatible.
AR# 60838
Date 08/28/2017
Status Active
Type General Article
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