Version Found: MIG 7 Series v2.0 Rev2
Version Resolved: See (Xilinx Answer 54025)
For MIG 7 Series v2.0 Rev2 RLDRAM3 designs the SIM_BYPASS_INIT_CAL parameter is always set to "FAST" in both <core_name>_mig.v and <core_name>_mig_sim.v by default.
"FAST" should only be used for behavioral simulations and will cause calibration and data failures in hardware.
For synthesis, implementation, and hardware testing SIM_BYPASS_INIT_CAL should be set to "NONE".
This issue affects RLDRAM3 designs only.
To work around this issue you must modify the top-level parameter SIM_BYPASS_INIT_CAL inside "<core_name>_mig.v" to the following:
06/09/2014 - Initial Release
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