Version Found: MIG 7 Series v2.1
Version Resolved: See (Xilinx Answer 54025)
Starting with v2.1, MIG 7 Series uses an increased IDELAYCTRL reference clock frequency for designs operating above 1333Mbps.
See (Xilinx Answer 60687) for details.
However, for Kintex -2L/-3L speed grades, a 400MHz reference clock is not supported.
Therefore, a DRC error is generated during implementation as follows:
To work around this, the parameter REF_CLK_MMCM_IODELAY_CTRL needs to be manually set to "FALSE" within the <module_name>_mig.v/.vhd and <module_name>_mig_sim.v/.vhd rtl files located within the user_design/rtl directory.
This will keep the pre-existing 200MHz refclk setting.
06/18/2014 - Initial Release