AR# 60848

Design Advisory for Zynq-7000 SoC: Static Memory Controller, Parallel (SRAM/NOR) Interface 64MB configuration issues

Description

In accordance with (UG585), the Static Memory Controller for Parallel (SRAM/NOR) Interface features:

  • One chip select (CS0) with up to 26 address signals (64MB)
  • Two chip selects (CS0/Cs1) with up to 25 address signals (32+32MB)

The first configuration (64MB) can be used by connecting MIO1 to address bit 25 (A25) of the Memory and setting slcr.MIO_PIN_01{L2_SEL} = 01 (which is Address Bit 25, Output).

There are two problems with this configuration:

  • #1: Chip Select 0 (CS0) does not go active when accessing an address in range 0xE4000000 - 0xE5FFFFFF.
  • #2: The logic of Address bit 25 is inverted: A25 is '1' when accessing 0xE2000000 - 0xE3FFFFFF and '0' when accessing 0xE4000000 - 0xE5FFFFFF.

Below is a summary of how the SMC works for NOR/SRAM:

slcr.MIO_PIN_01{L2_SEL}
Address Accessed
MIO0
MIO1
01 (ADDR25)
0xe200_0000
1->0->1 (acts as active CS0)
1 (acts as inverted ADDR25)
01 (ADDR25)
0xe400_0000
0 (acts as inactive CS0)
0 (acts as inverted ADDR25)
10 (CS1)
0xe200_0000
1->0->1 (acts as active CS0)
1 (acts as inactive CS1)
10 (CS1)
0xe400_0000
1 (acts as inactive CS0)
1->0->1 (acts as active CS1)
00 (GPIO)
0xe200_0000
1->0->1 (acts as active CS0)
1 (reset state, internal pull-up)
00 (GPIO)
0xe400_0000
1 (acts as inactive CS0)
1 (reset state, internal pull-up)
 

Solution

Please refer to these two ARs:

(Xilinx Answer 61637)Zynq-7000 SoC, SMC Parallel (SRAM/NOR) Interface Does Not Correctly Assert CS0 For 64 MB Memories
(Xilinx Answer 61638)Zynq-7000 SoC, SMC Parallel (SRAM/NOR) Interface Address Bit 25 Is Inverted For 64 MB Memories


AR# 60848
Date 05/28/2018
Status Active
Type Design Advisory
Devices