General Description: FPGA Express will insert I/O buffers and/or registers at the top level as long as the port is listed in the top-level port declaration. Is it possible to insert I/O ports at lower levels? Yes. Is it possible to insert I/O ports at the top level without declaring them as top level ports? Yes. This can be done by instantiating BOTH the PAD and the I/O buffer for the port.
When instantiating I/O pad/buffer combinations, do not list the port in the top level port declaration. You must also instantiate both the I/O buffer (or I/O flip flop) and the IPAD/OPAD. The IPAD/OPAD component has one pin, always called PAD.
When using a bidirectional signal, instantiate the IOPAD (pin name is IOPAD), input buffer, and output tri-state buffer.
In the examples below, a flip flop is inferred. The clock and reset come from the level above, and the DIN and DOUT pins are instantiated in this level.
library IEEE; use IEEE.std_logic_1164.all;
entity LOWER is port (CLK, RST : in STD_LOGIC); -- note that DIN and DOUT are not listed here end LOWER;
architecture lower_arch of LOWER is
signal DIN, DOUT: STD_LOGIC; -- ports DIN and DOUT are declared here signal DIN_INT, DOUT_INT: STD_LOGIC;
component IBUF port (I : in STD_LOGIC; O : out STD_LOGIC); end component ;
component IPAD port (PAD : out STD_LOGIC); -- note the direction is OUT end component ;
component OBUF port (I : in STD_LOGIC; O : out STD_LOGIC); end component ;
component OPAD port (PAD : in STD_LOGIC); -- note the direction is IN end component ;
clocked: process(CLK, RST) begin if (RST='1') then DOUT_INT <= '0'; elsif rising_edge(CLK) then DOUT_INT <= DIN_INT; end if; end process;
IBUF_inst: IBUF port map (I => DIN, O => DIN_INT);
IPAD_inst: IPAD port map (PAD => DIN);
OBUF_inst: OBUF port map (I => DOUT_INT, O => DOUT);
OPAD_inst: OPAD port map (PAD => DOUT);
module LOWER (CLK, RST) ; // note that DIN and DOUT are not listed here
input CLK, RST;
wire DIN, DIN_INT, DOUT; // ports DIN and DOUT are declared here reg DOUT_INT;
always @ (posedge CLK or posedge RST) begin if (RST) DOUT_INT = 1'b0; else DOUT_INT = DIN_INT; end
NOTE: FPGA Express will not recognize the IPAD and OPAD components because they are not in the synthesis libraries. You can ignore warnings like these:
Warning: Cell 'IPAD_inst': 'IPAD' is not a primitive for 'XC4000XL'. (FPGA-INTERNAL-xlx-8) Warning: Cannot link cell 'LOWER/IPAD_inst' to its reference design 'IPAD'. (FPGA-LINK-2) Warning: Cell 'OPAD_inst': 'OPAD' is not a primitive for 'XC4000XL'. (FPGA-INTERNAL-xlx-8) Warning: Cannot link cell 'LOWER/OPAD_inst' to its reference design 'OPAD'. (FPGA-LINK-2) Warning: The cell '/TOP-1/U1/IPAD_inst' is not linked to any design. (FPGA-CHECK-4) Warning: The cell '/TOP-1/U1/OPAD_inst' is not linked to any design. (FPGA-CHECK-4)
Check the PAD report from the Xilinx implementation tools to ensure that all your I/O have been connected properly. Remember that the final name of the port will include the hierarchical name if the port was instantiated at a lower level, so it will look like this in the pad report: