We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60907

2014.2 Vivado - Partial Reconfiguration - Nested Pblocks cause LUT1 buffers inserted during opt_design have no Pblock property


I create nested Pblocks in the RM to control placement and allow routing to complete. 

However, when nested Pblocks are added, the parent Pblock is no longer on the hierarchical cell marked as HD.RECONFIGURABLE, and the LUT1 buffers that are inserted during opt_design do not inherit the Pblock property.

This results in the following error in pre-place_design DRCs:

ERROR: [Drc 23-20] Rule violation (HDPR-1) Cells must have a Pblock defined - HD.RECONFIGURABLE primitive cell 'gpio/HD_PR_Connection_S_IN_BUF_gpio_csr_addr_i_dup1_10_' does not have a Pblock defined.  Please first define a Pblock for the HD.RECONFIGURABLE cell 'gpio' and define the range(s) for each primitive type.


The issue has been fixed in Vivado 2014.3.

The workaround is to add the pblock defining constraints after opt_design.

AR# 60907
Date 12/11/2014
Status Archive
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2014.1
Page Bookmarked