AR# 60923


Design Assistant for Vivado HLS : Understanding the Vivado HLS Design Flow


This Answer Record contains child answer records covering various aspects of the Vivado HLS design flow. 

The Answer Record provides the information to help you understand and get started with a Vivado High-Level Synthesis design flow. 

The resources below provide an introduction to FPGA using Vivado HLS, an overview of the steps in Vivado HLS and numerous design examples.

Note: This answer record is a part of the Xilinx Solution Center for Vivado HLS (Xilinx Answer 47428), which is available to address all questions related to Vivado HLS. 

Whether you are starting a new design or troubleshooting a problem, use the Solution Center for Vivado Synthesis to guide you to the right information. 


Vivado HLS Design Flow

For software engineers new to FGPA design and for FPGA design experts new to High-Level Synthesis (HLS), the Introduction to FPGA Design with Vivado HLS provides a complete background on FPGA devices, High-Level Synthesis and C modeling for hardware.

To get started using Vivado HLS, refer to the Vivado QuickTake video Getting Started with Vivado High-Level Synthesis. Details on using the Tcl interface are presented in the Vivado QuickTake video Using the Vivado HLS Tcl Interface.

Design Examples

The Vivado HLS Tutorial provides 10 tutorials covering every aspect of the Vivado HLS flow from simulating the C code to verification of the RTL design. 

The tutorial exercises also demonstrate how to integrate the Vivado HLS output IP into the rest of the system, including all steps to operate an IP block under processor control on a Zynq device. The location of the design files is noted at the start of each tutorial exercise.

The design flow to implement a Vivado HLS design in a Zynq device using Xilinx Platform Studio, ISE and SDK is detailed in the Application Note XAPP-1170. The location of the design files is noted at the start of the Application Note.

Application Note XAPP-1173 shows how a communications block is optimized with Vivado HLS and integrated into a System Generator for DSP design. The design files for this Application Note are located here.

In addition, a number of design and coding examples are provided with the Vivado HLS software. These can be accessed through the Welcome screen in the GUI or in the examples directory located in the Vivado HLS installation area.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47428 Xilinx Vivado HLS Solution Center N/A N/A
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 60923
Date 06/04/2014
Status Active
Type General Article
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