AR# 60925


Vivado HLS : Design Analysis and Optimization


This Answer Record contains child answer records covering the use and implementation of C code with Vivado HLS. The Answer Record explains where to get help with all aspects of design analysis and design optimization.


Note: This answer record is a part of the Xilinx Solution Center for Vivado HLS (Xilinx Answer 47428), which is available to address all questions related to Vivado HLS. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for Vivado Synthesis to guide you to the right information. 


Design Analysis

Before any design can be optimized, the exiting results must be analyzed. Vivado HLS provides both reports and a graphical analysis environment.

The Vivado HLS Tutorials provide a hands-on review of the reports in the tutorial High-Level Synthesis Introduction and an in-depth review of the graphical analysis feature is provided in the tutorial Design Analysis. 

Both of these topics are covered in the Vivado QuickTake video Analyzing your Vivado HLS Design.

For designers wishing to analyze the results using an RTL environment, the RTL Verification tutorial in the Vivado HLS Tutorial shows how automatic RTL testbench creation can be used to quickly create waveforms diagrams for cycle accurate analysis. 

An alternative is to open the Vivado HLS design inside Vivado. The final step in the tutorial High-Level Synthesis Introduction shows how a Vivado project file is automatically created.

Design Optimization

Each of the design optimizations which can be performed is explained in the Vivado Design Suite User Guide High-Level Synthesis. Refer to the chapter on Design Optimization for an overview.

Since I/O protocols are generally imposed on the block by outside connections it is recommended to select and define the I/O protocols before seeking to optimize the design: the IO protocols themselves may impose limitations on the optimization strategy. 

Vivado HLS can automatically add I/O protocols to the design through the Interface Synthesis feature.

An explanation of Interface Synthesis and I/O protocols in general is explained in the Vivado Design Suite User Guide High-Level Synthesis.

A tutorial on Interface Synthesis is provided in the Vivado HLS Tutorial

The tutorial titled Interface Synthesis reviews the basic of interface synthesis and shows how the interface can be optimized to create a design with higher performance.

Two complete tutorials on design optimization are provided in the Vivado HLS Tutorials.

The tutorial titled Design Analysis shows how the Analysis Perspective feature is used to analyze designs to determine how they can be optimized. 

The tutorial Design Optimization uses a matrix multiplier example to demonstrate the most common design optimization techniques using command directives and also demonstrates how changes to the C code are sometimes required for the most optimal RTL implementation.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47428 Xilinx Vivado HLS Solution Center N/A N/A
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 60925
Date 06/04/2014
Status Active
Type General Article
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