AR# 60926


Vivado HLS : RTL Verification


This Answer Record contains child answer records covering the use and implementation of C code with Vivado HLS. The Answer Record explains where to get help with all aspects of design analysis and design optimization.


Note: This answer record is a part of the Xilinx Solution Center for Vivado HLS (Xilinx Answer 47428), which is available to address all questions related to Vivado HLS. 

Whether you are starting a new design or troubleshooting a problem, use the Solution Center for Vivado Synthesis to guide you to the right information. 


Vivado HLS can automatically verify the RTL using simulation, if a C test bench is provided. 

Vivado HLS uses the C test bench to automatically generate an RTL test bench. 

You are highly encouraged to understand the importance of the C test bench by reviewing the section on C test benches in the High-Level Synthesis Coding Styles chapter of the Vivado Design Suite User Guide High-Level Synthesis - RTL verification is only meaningful when the C test bench checks the results.

The process for verifying the RTL is shown in the Vivado QuickTake video Verifying your Vivado HLS Design.

Finally, a tutorial on RTL verification is provided in the Vivado HLS Tutorials.

Three tutorial exercises show how the RTL can be verified, how an RTL simulator can be selected for the verification and how waveform trace files can be created, viewed and analyzed.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47428 Xilinx Vivado HLS Solution Center N/A N/A
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 60926
Date 06/04/2014
Status Active
Type General Article
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