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AR# 60949

2014.2 - Zynq BFM example design fails simulation in VCS and IES

Description

VCS simulator fails when simulating the Zynq BFM Example design with the following Error:

Error-[STASKEC_USF] Undefined system function /proj/xbuilds/2014.2_0422_1/installs/lin64/Vivado/2014.2/data/secureip/axi_bfm/cdn_axi3_master_bfm.vp, 



NCSim fails when simulating the Zynq BFM Example design with the following Error:
 

Child process exited abnormally

Solution

There is an issue with export_simulation not passing the necessary switch to load BFM libraries.

A work-around is to edit the .sh file delivered by export_simulation.

ncsim_opts="-64bit -logfile tb_sim.log -loadvpi $XILINX_VIVADO//lib/lnx64.o/libxil_ncsim:xilinx_register_systf.xilinx_register_systf"

vcs_opts="-full64 -debug_pp -t ps -licwait -60 -l tb_comp.log -load $XILINX_VIVADO//lib/lnx64.o/libxil_vcs.so:xilinx_register_systf


In 2014.3, unified simulation flow will be introduced and the issue will be fixed in that flow.
AR# 60949
Date Created 06/04/2014
Last Updated 01/21/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1