Version Found: RLDRAM3 v5.0 (Rev. 1), QDRII+ v5.0 (Rev .1)
Version Resolved: See (Xilinx Answer 69037) for RLDRAM3, See (Xilinx Answer 69038) for QDRII+
The following path can fail timing for MIG UltraScale RLDRAM3 and QDRII+ designs as a result of a long route delay.
If this exact path fails timing please open a Service Request with Xilinx Technical Support.
Revision History:
06/04/2014 - Initial Release
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
69037 | UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues | N/A | N/A |
69038 | UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues | N/A | N/A |
AR# 60951 | |
---|---|
Date | 12/15/2017 |
Status | Active |
Type | Known Issues |
Devices | |
Tools | |
IP |