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AR# 60975

2014.2 Vivado IP Flows - IP cores within a user IP result in implementation errors saying that the IP is a black box

Description

I have a Vivado project that contains Xilinx IP.

After making sure the project implements as expected, I package this project using the "Package your current project" option for "Create and package IP"

My new user IP is created successfully and added to the IP Catalog.

However, when I use my new IP in a Vivado Project design (For Example: in a Block Diagram) the customized IP core within my user IP core appears to stay a black box.

Synthesis completes but makes this core a black box. From the synthesis report I can see an "INFO" message similar to the following:

[Synth 8-637] synthesizing blackbox instance 'my_ram_inst' of component 'blk_mem_gen_0' [my_IP_top.vhd":81]


Implementation fails with black box related errors similar to the following:

[Opt 31-30] Blackbox design_1_i/my_IP_top_0/U0/my_ram_inst (blk_mem_gen_0) is driving pin I of primitive cell interface_bram_1_dout_OBUF[10]_inst. This black box cannot be found in the existing library.


Why does this occur and how can this be avoided?

Solution

This has black box problem has been seen in the following situations.

The original IP core is instantiated as a black box in the packaged project. 

If the output targets for the IP core are generated with the OOC option selected (the default option that creates a DCP for the IP core) then the instantiation template for the IP core will include blackbox attributes.

For Example:

ATTRIBUTE SYN_BLACK_BOX : BOOLEAN;
ATTRIBUTE SYN_BLACK_BOX OF blk_mem_gen_0 : COMPONENT IS TRUE;
ATTRIBUTE BLACK_BOX_PAD_PIN : STRING;
ATTRIBUTE BLACK_BOX_PAD_PIN OF blk_mem_gen_0 : COMPONENT IS "clka,rsta,ena,wea[0:0],addra[3:0],dina[15:0],douta[15:0],clkb,rstb,enb,web[0:0],addrb[3:0],dinb[15:0],doutb[15:0]";

This is not an issue for the original project because the OOC module for the IP core is picked up and used in Implementation.  

However, if the project is packaged and used in a Block Design (BD) then the OOC module is ignored (DCPs within a BD are not supported).  

Because of the black box attributes, the HDL file(s) delivered for IP core will be ignored by synthesis and because the OOC is not used, Implementation fails due to the missing module.

To correct this problem, the black box attributes should be deleted (not just commented out) from the instantiating HDL before the project is packaged in IP Packager.

 


The packaged IP project does not include the generated HDL file under the synth directory for the "IP File Group"

When packaging a project containing an IP core a user can select one of the following two options for IP cores within the project

  • Include generated files
  • Include XCI

The "Include XCI" option should be selected.  

The .xci file for the IP core will be included in the packaged IP and will reference all other files required for the IP core.

Note: It has been discovered that if the "Include generated files" option is used, not all file for an IP core (Specifically files in the IP/synth directory) are included in the IP File Group.

After re-packaging and re-generating the user IP, remove the original IP core from the Vivado project and add a new modified version.

To ensure that this has worked, go to the Sources panel in the Vivado project and expand the IP source. 

All sources should be referenced and none should contain a question mark.

 

Within a block diagram, a user can check to see if they have the correct version of a packaged IP project by right clicking on the IP instance in the BD and selecting "Edit in IP Packager".

 


 

Linked Answer Records

Associated Answer Records

AR# 60975
Date Created 06/04/2014
Last Updated 06/25/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2