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AR# 60986

Artix-7/Kintex-7/Virtex-7 - 7 Series Integrated Block Wrapper for PCI Express v3.0 - Example Design fails simulation in 3rd party simulator when using pre-compiled libraries that are compiled in project mode

Description

When simulating with a 7 Series Integrated Block Wrapper for PCI Express v3.0 core using the default steps, errors can be observed in the simulator.

For example, when targeting the Artix-7 PCIe example design using the following steps:
 

ModelSim:
 
1. Open the example project
2. From the Tcl Console, run the compile_simlib command to compile simulation libraries for the target simulator
3. Change Simulation Settings to set the target simulator to ModelSim
4. From the Flow Navigator, click Run Simulation to launch ModelSim
 
IES/VCS:
 
1. Open the example project
2. From the Tcl Console, run the compile_simlib command to compile simulation libraries for the target simulator
3. From the Tcl Console, run the export_simulation command
4. Execute the simulation script
 
Using this flow targeting Artix-7, the simulation will error out with messages complaining about the GTXE2 model:
 
ModelSim:
 

# ** */2014.1/data/verilog/src/unisims/GTXE2_CHANNEL.v(3423): Module 'B_GTXE2_CHANNEL' is not defined.

 
IES:
 

ncelab: *E,CUVMUR (*/2014.1/data/verilog/src/unisims/GTXE2_CHANNEL.v,3191|23): instance ':board(rtl):RP@xilinx_pcie_2_1_rport_7x(rtl):rport@pcie_2_1_rport_7x(pcie_7x):gt_top_i@pcie_7x_0_gt_top(pcie_7x):
pipe_wrapper_i@pcie_7x_0_pipe_wrapper<module>.pipe_lane[0].gt_wrapper_i@pcie_7x_0_gt_wrapper<module>
.gtx_channel.gtxe2_channel_i@GTXE2_CHANNEL<module>.B_GTXE2_CHANNEL_INST' of design unit 'B_GTXE2_CHANNEL' is unresolved in 'unisims_ver.GTXE2_CHANNEL:module'.

 
VCS_MX:
 

######   Error - [URMI] Unresolved modules
*/data/verilog/src/unisims/GTXE2_CHANNEL.v, 3191
"B_GXE2_CHANNEL_INST


Similar messages can be observed for B_GTPE2_CHANNEL or B_GTHE2_CHANNEL when targeting Kintex-7 or Virtex-7
 

Solution

When compile_simlib is run with a project open, the tool will use the device family, target language, and library settings specified by the project as the default values.
 
The default with no project open is to generate the library for all families.

All 3 GT primitive types (GTP, GTX, GTH) are instantiated in the PCIe GT wrapper, but are only enabled based on the device architecture.
 
The problem is that the simulator needs the models of all 3 GT primitive types when simulating the Artix-7 PCIe example design.

In the above example, the library was generated when the project was opened.

However, the library was only generated for that architecture, and as a result the simulator errors out.
 
The Solution is to specify "-family all" when running compile_simlib so that it generates libraries for all device families.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58884 Xilinx Simulation Solution Center - Design Assistant - IP Simulation N/A N/A

Associated Answer Records

AR# 60986
Date Created 06/05/2014
Last Updated 04/17/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite
IP
  • 7 Series Integrated Block for PCI Express (PCIe)