AR# 60992


MIG 7 Series RLDRAM3 - Simulation - Calibration failures due to issue with memory model


Version Found: MIG 7 Series v2.0 Rev 3
Version Resolved: See (Xilinx Answer 54025)

At high frequency it is possible for calibration to fail as a result of different phase alignments between the read clock (QK/QK#) and read data (DQ) in the memory model and during calibration.

This is an issue with the Micron memory model and only occurs at higher frequencies. 


This issue only affects behavioral simulations and can be safely ignored as this will not cause problems in hardware.

If a work around is needed please contact Micron or open a webcase with Xilinx Technical Support.

Revision History

06/09/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 60992
Date 06/06/2014
Status Active
Type Known Issues
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