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AR# 61027

Vivado Synthesis - The "Block RAM" Table in Synthesis report doesn't reflect all BRAMs used in design

Description

In the "Block RAM" Table in the Synthesis report, not all BRAMs used in the design are listed.


For example, the below design has 4 BRAMs but only 3 of them are reported in the table.

Is this expected behavior?
 
(see table below)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
---------------------------------------------------------------------------------
Start RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
 
Block RAM:
+------------------------------+----------------+-----------------------------------+---+---+----------------------------------+----+---+-------------------+-------------+-------------+---------------------------------------------+
|Module Name   ------     | RTL Object | PORT A (depth X width)   | W | R | PORT B (depth X width)  | W | R | OUT_REG      | RAMB18 | RAMB36 | Hierarchical Name                         | 
+------------------------------+----------------+-----------------------------------+---+---+----------------------------------+----+---+-------------------+-------------+-------------+---------------------------------------------+
|generic_mem_medium | mem_reg     | 64 X 72(WRITE_FIRST)   | W |    | 64 X 72(WRITE_FIRST)   |     | R | Port A and B   | 0              | 1             | generic_mem_medium/extram       | 
|generic_mem_small     | mem_reg     | 16 X 72(WRITE_FIRST)   | W |    | 16 X 72(WRITE_FIRST)   |     | R | Port A and B   | 0              | 1             | generic_mem_small/extram__1     | 
|generic_mem_medium | mem_reg     | 64 X 72(WRITE_FIRST)   | W |    | 64 X 72(WRITE_FIRST)   |     | R | Port A and B   | 0              | 1             | generic_mem_medium/extram__2 | 
+------------------------------+----------------+-----------------------------------+---+---+----------------------------------+----+---+-------------------+-------------+-------------+---------------------------------------------+
 

Solution

This is intended behavior.

It is not intended to report RAM per instance, but per module.

So multiple instantiated RAMs are reported only once.

Therefore you may see less BRAMs reported in this table than what the design has.

 
There is also a note after the table that explains this.

Note: The table shows RAMs generated at current stage.

Some RAM generation could be reversed due to later optimizations.

Multiple instantiated RAMs are reported only once.

"Hierarchical Name" reflects the hierarchical modules names of the RAM and only part of it is displayed.
 
To report the BRAM utilization in the design, refer to "Report Cell Usage" Table in the Synthesis report or go to the Utilization report (report_utilization)
AR# 61027
Date Created 06/06/2014
Last Updated 06/06/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite