We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61030

Vivado Synthesis - "ERROR: [Synth 8-26]" is given when SystemVerilog file with a struct type instantiates VHDL with a port of record type


Vivado Synthesis gives the following error when a struct type signal in a SystemVerilog file is connected to a port of record type of a VHDL submodule.

ERROR: [Synth 8-26] instantiation from verilog of vhdl entity with complex port types not implemented [xxx/top.sv:17]

Below is an example code of this case.

SystemVerilog (top module):
import verilog_package::*;
module top (in1, in2, out1, out2);
verType temp;        //verType is a struct
bottom u0 (.in1(temp), .out1(out1), .out2(out2));

VHDL (submodule):

library work;
use work.vhdl_package.all;
entity bottom is port (
in1 : in vhdlType;     --vhdlType is a record
out1 : out std_logic_vector(4 downto 0);
out2 : out std_logic);
end bottom;

architecture beh of  bottom is 
out1 <= in1.a;
out2 <= in1.b;
end beh;


Although the SystemVerilog struct type and VHDL record type actually match up, this kind of coding style is currently not supported.

This will be supported in a future release.
AR# 61030
Date 06/11/2014
Status Active
Type Known Issues
  • Vivado Design Suite
Page Bookmarked