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AR# 61063

Vivado HLS 2014.2: Debug Guide for investigating C/RTL co-simulation issues

Description

The Vivado HLS C/RTL co-simulation feature uses the user C test bench and generated RTL to confirm that the RTL simulation matches the behavior of the C, C++ or SystemC source code.

When the C/RTL co-simulation fails, the following message is issued.
 

@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***


This Answer Record contains a downloadable PDF with steps to investigate and a debug guide for use when there is an issue with the Vivado HLS C/RTL co-simulation flow.

Solution

Answer Records are Web-based content that are updated as new information becomes available.

To obtain the latest version of the PDF, visit this answer record.

 

Revision History

09/09/2014 Initial Release

Attachments

Associated Attachments

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 61063
Date Created 06/09/2014
Last Updated 09/09/2014
Status Active
Type Solution Center
Tools
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite
  • Vivado Design Suite - 2014.1