AR# 61075


MIG UltraScale - What is the recommended flow for creating multiple MIG interfaces within a single design?


MIG UltraScale does not have an option to select multiple controllers similar to the MIG 7-Series tool.

This answer record details the recommended steps for adding multiple MIG UltraScale interfaces within a single design. 


Support Plan

For UltraScale MIG, multi-controller support through the MIG tool will not be added.

Changes to the I/O pin planning flow for memory interfaces are coming in a future release that will streamline the usage of multiple MIG instances. 

However, until these I/O pin planning changes are released,
MIG needs to be run multiple times to create unique cores with the target I/O assignments.

Notes on IO Pin Planning Changes
I/O pin planning is moving out of MIG UltraScale and into Vivado I/O Pin Planner in a future release. 

This will allow easy pin planning, including clock pin planning for multiple instances of MIG IP cores outside of MIG.

It will additionally remove the I/O XDC constraints from the MIG IP into a top-level XDC file. 

This removes the need to regenerate MIG cores any time a memory interface pin change is needed and the inability to reuse the same IP multiple times.

Current Multi-Controller Support Flow

  1. Generate each of the required MIG controllers independently.
    Manually ensure that all Pin Requirements documented in PG150 are met and pins do not overlap.
    Use of the MIG I/O Planner to manually assign pins may be required to get the exact pinout required and pack the banks as needed.

  2. Upon generation, leave the default settings in place for "Generate Output Products" which enables OOC flow and therefore runs Synthesis on the generated core.

  3. Create a top-level wrapper file that instantiates the generated IP and connects them to the user design.
    Ensure that the ports are unique for each controller. 
    For example: c0_ddr4_*, c1_ddr4_*, c2_ddr4_*.

  4. When the MIG IP are located within the same column, create a top-level XDC file. 
    Copy and paste the BUFGCE constraints for each core into the top-level XDC.
    Add the appropriate hierarchy of the unique MIG IP instance into the NAME = path. 

    For example:
    For pre-2014.4:

    set_property LOC BUFGCE_X0Y22 [get_cells -hier -filter {NAME =~ u_mig_0*/u_ddr4_phy/u_infrastructure/mmcm_pll_loop[0].CENTER_MMCM.u_bufg_divClk}]
    set_property LOC BUFGCE_X1Y94 [get_cells -hier -filter {NAME =~ u_mig_1*/u_ddr4_phy/u_infrastructure/mmcm_pll_loop[0].CENTER_MMCM.u_bufg_divClk}]

    For 2014.4 (due to directory change to support PHY Only):

    set_property LOC BUFGCE_X0Y46  [get_cells {u_mig_0/inst/u_ddr3_mem_intfc/u_mig_ddr3_phy/inst/u_ddr3_pll_rst/u_bufg_divClk }]
    set_property LOC BUFGCE_X0Y71  [get_cells {u_mig_1/inst/u_ddr3_mem_intfc/u_mig_ddr3_phy/inst/u_ddr3_pll_rst/u_bufg_divClk }]
    set_property LOC BUFGCE_X1Y93  [get_cells {u_mig_2/inst/u_ddr3_mem_intfc/u_mig_ddr3_phy/inst/u_ddr3_pll_rst/u_bufg_divClk }]
    set_property LOC BUFGCE_X1Y116 [get_cells {u_mig_3/inst/u_ddr3_mem_intfc/u_mig_ddr3_phy/inst/u_ddr3_pll_rst/u_bufg_divClk }]

    The Y coordinates of these BUFGCE constraints need to be adjusted. 
    See (Xilinx Answer 61076) for details on the required change.

  5. Copy and paste the create_clock constraints for each core into the top-level XDC.
    Add the appropriate hierarchy of the unique MIG IP instance into the -name path.

  6. For example:
    create_clock -name u_mig_0*/c0_sys_clk -period 10.0 [get_ports c0_sys_clk_p]
    create_clock -name u_mig_1*/c0_sys_clk -period 10.0 [get_ports c0_sys_clk_p]

6.   Run through Synthesis and Implementation.

Clock Sharing Considerations
Please see (Xilinx Answer 61304) for details.
This will likely lead to manually editing the generated MIG IP to allow the sharing of clocking resources.
For information on how to manually modify IP cores in Vivado, see (Xilinx Answer 57546).

Related Information:
(Xilinx Answer 61076) MIG UltraScale - Multiple instances of MIG IP fail with "[Place 30-678] Failed to do clock region partitioning"

AR# 61075
Date 11/24/2014
Status Active
Type General Article
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