AR# 61076


UltraScale Memory IP - Multiple instances of MIG IP fail with "[Place 30-678] Failed to do clock region partitioning"


Version Found: v5.0 Rev1

Version Resolved: See (Xilinx Answer 58435)

When using multiple instances of the MIG UltraScale IP, you might see the following error during implementation:

ERROR: [Place 30-678] Failed to do clock region partitioning: Clock partitioning failed to resolve contention in clock region X2Y4. The following clock nets need to use the same clock routing track, as their clock buffer sources are locked to BUFGCE sites that use the same track. The initial regions, where loads of these clocks are placed at, intersect with each other, forcing the clock partitions for these clocks to overlap. This creates contention on the clock routing tracks, but clock region partitioning failed to resolve these contentions. If the clock buffers need to be locked, we recommend users constrain them to a clock region and not to a specific BUFGCE site. If clock sources should be locked to specific BUFGCE sites that share the same routing tracks, make sure loads of such clocks are not constrained to the same region(s). Clock nets in the congested region(s):


To work around this error, follow the steps below:

1) Open the <mig_core_name>.xdc of any of the MIG instances in contention noted in the error message.

2) Find the BUFGCE LOC Constraints for all of the MIG instances. 

They should look similar to the following:

set_property LOC BUFGCE_X#Y## [get_cells -hier -filter {NAME =~ */u_ddr4_phy/u_infrastructure/mmcm_pll_loop[0].CENTER_MMCM.u_bufg_divClk}]

3) The offset on the Y coordinates cannot be a multiple of 24. Identify BUFGCEs that are offset by a multiple of 24.

For example:

set_property LOC BUFGCE_X1Y93     [get_cells {u_mig_1/inst/u_ddr4_mem_intfc/u_ddr4_phy/u_infrastructure/mmcm_pll_loop[1].CENTER_MMCM.u_bufg_divClk}]
set_property LOC BUFGCE_X1Y117  [get_cells {u_mig_0/inst/u_ddr4_mem_intfc/u_ddr4_phy/u_infrastructure/mmcm_pll_loop[1].CENTER_MMCM.u_bufg_divClk}]

4) Decrement the Y# coordinate by 1 on the BUFGCE that includes the smaller of the two Y coordinates. 

For the example above, replace the following text:


set_property LOC BUFGCE_X1Y93 [get_cells -hier -filter {NAME =~ */u_ddr4_phy/u_infrastructure/mmcm_pll_loop[0].CENTER_MMCM.u_bufg_divClk}]

New text:

set_property LOC BUFGCE_X1Y92 [get_cells -hier -filter {NAME =~ */u_ddr4_phy/u_infrastructure/mmcm_pll_loop[0].CENTER_MMCM.u_bufg_divClk}]

Note: For more than 2 instances, ensure that the Y coordinates are never offset by a multiple of 24.

When a multiple of 24 offset exists, decrement the smaller of the two by one as noted in Step 4.

In rare cases it may be required to LOC down the entire clocking structure for each instance of MIG to bypass the error message.

Below is an example for a MIG DDR4 instance:

et_property LOC PLLE3_ADV_X0Y3 [get_cells{port_mem_inst/GEN_LAT1_DDR_MEM_IF_ON.MEM_IF/inst/u_ddr4_mem_intfc/u_ddr4_phy/u_infrastructure/mmcm_pll_loop[1].CENTER_MMCM.PLLE3_BASE_INST_CENTRE}]
set_property LOC PLLE3_ADV_X0Y1 [get_cells {port_mem_inst/GEN_LAT1_DDR_MEM_IF_ON.MEM_IF/inst/u_ddr4_mem_intfc/u_ddr4_phy/u_infrastructure/mmcm_pll_loop[0].OTHER_PLL.PLLE3_BASE_INST_OTHER}]
set_property LOC MMCME3_ADV_X0Y1 [get_cells {port_mem_inst/GEN_LAT1_DDR_MEM_IF_ON.MEM_IF/inst/u_ddr4_mem_intfc/u_ddr4_phy/u_infrastructure/mmcm_pll_loop[1].CENTER_MMCM.CENTER_MMCM_ADDN_CLK_ENABLE.mmcme3_adv_inst}]
set_property LOC BUFGCE_X0Y26 [get_cells {port_mem_inst/GEN_LAT1_DDR_MEM_IF_ON.MEM_IF/inst/u_ddr4_mem_intfc/u_ddr4_phy/u_infrastructure/mmcm_pll_loop[1].CENTER_MMCM.u_bufg_divClk_0}]
set_property LOC BUFGCE_X0Y45 [get_cells {port_mem_inst/GEN_LAT1_DDR_MEM_IF_ON.MEM_IF/inst/u_clk_ibuf/u_bufgce}]

Revision History:
09/09/2014 - Updated LOC requirements

07/22/2014 - Updated BUFGCE steps.
06/10/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions N/A N/A
AR# 61076
Date 01/19/2018
Status Active
Type Known Issues
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