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  4. AR# 61087: 2014.2 Vivado IP Release Notes - All IP Change Log Information

AR# 61087

2014.2 Vivado IP Release Notes - All IP Change Log Information

Description

This answer record contains a comprehensive list of IP change log information from Vivado 2014.2 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

Solution

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32-bit Initiator/Target for PCI (7-Series) (5.0)
 * Version 5.0 (Rev. 4)
 * No changes.

3GPP LTE Channel Estimator (2.0)
 * Version 2.0 (Rev. 5)
 * Product Brief renamed from xmp to pb.

3GPP LTE MIMO Decoder (3.0)
 * Version 3.0 (Rev. 5)
 * Product Brief renamed from xmp to pb.

3GPP LTE MIMO Encoder (4.0)
 * Version 4.0 (Rev. 5)
 * Product Brief renamed from xmp to pb.

3GPP Mixed Mode Turbo Decoder (2.0)
 * Version 2.0 (Rev. 5)
 * Internal change management process enhancements, no functional changes.

3GPP Turbo Encoder (5.0)
 * Version 5.0 (Rev. 4)
 * No changes.

3GPPLTE Turbo Encoder (4.0)
 * Version 4.0 (Rev. 4)
 * No changes.

64-bit Initiator/Target for PCI (7-Series) (5.0)
 * Version 5.0 (Rev. 4)
 * No changes.

7 Series FPGAs Transceivers Wizard (3.3)
 * Version 3.3
 * Added support for rf900 package for defense-grade(XQ) Zynq 7045.
 * Added logic to keep CPLL/QPLL in powerdown until reference clock is available.
 * Fixed multiple reset issue for GTH/GTP.
 * Modified constraint files for false paths(Design Advisory 60356)

7 Series Integrated Block for PCI Express (3.0)
 * Version 3.0 (Rev. 2)
 * Added AZynq7030 device support.
 * Added QArtix 50t device support.
 * Enabled PIPE simulation and External PIPE interface support only when shared logic option Shared Logic (clocking) in example design is selected.

AHB-Lite to AXI Bridge (3.0)
 * Version 3.0 (Rev. 1)
 * Example design XDC update for timing DRC
 * Updated Example design to use Clocking Wizard to generate clocks.

AXI 10G-Ethernet (1.2)
 * Version 1.2 (Rev. 1)
 * Fixed the transceiver reset logic in VHDL projects (Verilog projects had no issue).
 * Fixed the 1-step logic so that correction Field modification can occur in an earlier byte position within the frame.  This will allow 1-step modification of layer 2 packets in addition to IPv UDP packets.
 * Adjusted the 64-bit fractional nanoseconds field pipelining logic to ease timing closure.
 * Updated to use the latest version of the underlying xlconstant subcore, no functional changes.

AXI AHBLite Bridge (3.0)
 * Version 3.0 (Rev. 1)
 * Example design XDC update for timing DRC.

AXI APB Bridge (3.0)
 * Version 3.0 (Rev. 1)
 * Example design XDC updated, no functional changes.

AXI BFM Cores (5.0)
 * Version 5.0 (Rev. 3)
 * Improved GUI speed and responsiveness, no functional changes.

AXI BRAM Controller (4.0)
 * Version 4.0 (Rev. 1)
 * Constrained the range for the variable "size_plus_lsb" between 1 to 256 in narrow.vhd file to improve the timing.
 * Re-Packaged to improve internal automation, no functional changes.

AXI CAN (5.0)
 * Version 5.0 (Rev. 5)
 * Repackaged to correct simulation file set mapping, no functional changes.

AXI Central Direct Memory Access (4.1)
 * Version 4.1 (Rev. 3)
 * Example design XDC updated to remove the create_clock constraint.
 * No functional changes.

AXI Chip2Chip Bridge (4.2)
 * Version 4.2 (Rev. 1)
 * Updated example design I/O constraints.

AXI Clock Converter (2.1)
 * Version 2.1 (Rev. 2)
 * No changes.

AXI Crossbar (2.1)
 * Version 2.1 (Rev. 3)
 * Fixed IP integrator support when all read or write connectivity parameters are set to manual override.

AXI Data FIFO (2.1)
 * Version 2.1 (Rev. 2)
 * No changes.

AXI Data Width Converter (2.1)
 * Version 2.1 (Rev. 2)
 * No changes.

AXI DataMover (5.1)
 * Version 5.1 (Rev. 3)
 * Example design XDC updated to remove the create_clock constraint.
 * No functional changes.

AXI Direct Memory Access (7.1)
 * Version 7.1 (Rev. 3)
 * Example design XDC updated to remove the create_clock constraint.
 * Repackaged to improve internal automation, no functional changes.
 * No functional changes

AXI EMC (3.0)
 * Version 3.0 (Rev. 1)
 * Fixed the core to respond correctly for wvalid throttling (Xilinx Answer 59967).
 * Updated the parity calculation logic for narrow reads in Synchronous memories ((Xilinx Answer 60065).
 * Updated the RTL for incorrect parameter calculations, no functional changes.
 * Updated the example design to support all the allowable memory combinations.

AXI EPC (2.0)
 * Version 2.0 (Rev. 5)
 * Updated Example design XDC for timing DRC.
 * Updated upgrade utils file, no functional changes.

AXI Ethernet (6.1)
 * Version 6.1 (Rev. 1)
 * Support latest GT version.

AXI Ethernet Buffer (2.0)
 * Version 2.0 (Rev. 4)
 * Updated board flow commands in sync with internal flow updates, no functional changes.
 * Support minimum IFG + PREAMBLE length equal to 12 byte times at 1000 MHz.

AXI Ethernet Clocking (2.0)
 * Version 2.0 (Rev. 1)
 * No changes

AXI EthernetLite (3.0)
 * Version 3.0 (Rev. 1)
 * Repackaged to improve internal automation, no functional changes.
 * Example design XDC update for timing DRC.
 * Updated board flow commands in sync with internal flow updates, no functional changes.

AXI GPIO (2.0)
 * Version 2.0 (Rev. 5)
 * Example design XDC update for timing DRC.
 * Updated board flow commands in sync with internal flow updates, no functional changes.

AXI HWICAP (3.0)
 * Version 3.0 (Rev. 5)
 * Minor changes to GUI, no functional changes.

AXI IIC (2.0)
 * Version 2.0 (Rev. 5)
 * Example design XDC update for timing DRC.
 * Updated board flow commands in sync with internal flow updates, no functional changes.

AXI Interconnect (2.1)
 * Version 2.1 (Rev. 3)
 * No changes to interconnect features; revision level changes of interconnect subcores.

AXI Interrupt Controller (4.1)
 * Version 4.1 (Rev. 1)
 * No changes

AXI MMU (2.1)
 * Version 2.1
 * No changes

AXI Master Burst (2.0)
 * Version 2.0 (Rev. 4)
 * No changes

AXI Master Lite (3.0)
 * Version 3.0 (Rev. 4)
 * No changes

AXI Memory Mapped To PCI Express (2.4)
 * Version 2.4
 * Added AZynq7030 device support.
 * Added QArtix 50t device support.
 * Enabled External PIPE interface support only when shared logic option "Shared Logic (clocking) in example design" is selected.
 * Removed axi_aclk, axi_ctl_aclk input pins.
 * Fixed IPI issue of 62.5Mhz output clock for x1gen1 64-bit configuration.
 * Added support for 125Mhz Reference clock frequency.

AXI Memory Mapped to Stream Mapper (1.1)
 * Version 1.1 (Rev. 2)
 * No changes.

AXI Performance Monitor (5.0)
 * Version 5.0 (Rev. 3)
 * Issue of handling read/write requests at the same clock fixed.
 * Minimum/Maximum Write/Read latency registers are made available in profile mode.

AXI Protocol Checker (1.1)
 * Version 1.1 (Rev. 3)
 * Increased default MAX_xx_BURSTS to 8 (from 2); improved message text for CAM overflow.

AXI Protocol Converter (2.1)
 * Version 2.1 (Rev. 2)
 * No changes.

AXI Quad SPI (3.2)
 * Version 3.2 (Rev. 1)
 * GUI related updates.
 * Minor edits to RTL to delete redundant comments.
 * There are no functional changes.

AXI Register Slice (2.1)
 * Version 2.1 (Rev. 2)
 * No changes.

AXI TFT Controller (2.0)
 * Version 2.0 (Rev. 5)
 * Updated tool tip for Default I2C address parameter in GUI. no functional change.

AXI Timebase Watchdog Timer (2.0)
 * Version 2.0 (Rev. 5)
 * Updated Example design XDC for timing DRC, no functional changes.

AXI Timer (2.0)
 * Version 2.0 (Rev. 5)
 * Updated Example design XDC for timing DRC, no functional changes.

AXI Traffic Generator (2.0)
 * Version 2.0 (Rev. 3)
 * Code clean up, no functional changes.

AXI UART16550 (2.0)
 * Version 2.0 (Rev. 5)
 * Example design XDC updated.

AXI USB2 Device (5.0)
 * Version 5.0 (Rev. 3)
 * Updated XDC constraints for example design, no functional changes.

AXI Uartlite (2.0)
 * Version 2.0 (Rev. 5)
 * Example design XDC updated.
 * Minor GUI related updates, no functional changes.

AXI Video Direct Memory Access (6.2)
 * Version 6.2 (Rev. 1)
 * Example design XDC update for timing DRC.

AXI Virtual FIFO Controller (2.0)
 * Version 2.0 (Rev. 5)
 * Repackaged to improve internal automation, no functional changes.

AXI-Stream FIFO (4.0)
 * Version 4.0 (Rev. 5)
 * Repackaged to improve internal automation, no functional changes.

AXI4-Stream Accelerator Adapter (2.1)
 * Version 2.1 (Rev. 1)
 * Improved GUI speed and responsiveness.
 * Enabled inout scalar selection independent of input/output arguments.

AXI4-Stream Broadcaster (1.1)
 * Version 1.1 (Rev. 2)
 * No changes.

AXI4-Stream Clock Converter (1.1)
 * Version 1.1 (Rev. 3)
 * Updated to FIFO Generator v12.0.

AXI4-Stream Combiner (1.1)
 * Version 1.1 (Rev. 2)
 * No changes.

AXI4-Stream Data FIFO (1.1)
 * Version 1.1 (Rev. 3)
 * Updated to FIFO Generator v12.0.

AXI4-Stream Data Width Converter (1.1)
 * Version 1.1 (Rev. 2)
 * No changes.

AXI4-Stream Interconnect (2.1)
 * Version 2.1 (Rev. 3)
 * Improved handling of ARB_ON_TLAST parameter.

AXI4-Stream Protocol Checker (1.1)
 * Version 1.1 (Rev. 2)
 * No changes.

AXI4-Stream Register Slice (1.1)
 * Version 1.1 (Rev. 2)
 * No changes.

AXI4-Stream Subset Converter (1.1)
 * Version 1.1 (Rev. 2)
 * No changes.

AXI4-Stream Switch (1.1)
 * Version 1.1 (Rev. 3)
 * Repackaged with latest IP Packager; no functional changes.

AXI4-Stream to Video Out (3.0)
 * Version 3.0 (Rev. 4)
 * No changes.

Accumulator (12.0)
 * Version 12.0 (Rev. 4)
 * No changes.

Adder/Subtracter (12.0)
 * Version 12.0 (Rev. 4)
 * No changes.

Asynchronous Sample Rate Converter (2.0)
 * Version 2.0 (Rev. 3)
 * No changes.

Aurora 64B66B (9.2)
 * Version 9.2 (Rev. 1)
 * UltraScale GT Wizard version upgrade.
 * Fixed Simplex designs with error as Failed to open info file xil_defaultlib/_info in read mode.
 * PMA_RSV attribute setting updated for 7-Series GTH designs.
 * Fixed hold violation timing issues in UltraScale device based designs
 * Added missing synchronizers in clocking core for UltraScale designs.
 * GT_DIRECTION set as BOTH,TX_ENABLE & RX_ENABLE set as TRUE for UltraScale designs.

Aurora 8B10B (10.2)
 * Version 10.2 (Rev. 1)
 * UltraScale GT Wizard version change.
 * Added support for XQ7Z045 RF900 devices.
 * Fixed hold violation timing issues in UltraScale device based designs.
 * Updated channel bonding levels logic for >= 13 lanes in 4 byte mode.
 * Fixed gt0_dmonitorout_out port width for GTX devices in transceiver debug ports.
 * Free running INIT CLK is connected to VIO core in example design.
 * Fixed latch inference issue in crc modules for VHDL designs.
 * Updated CLK_COR_MIN_LAT and CLK_COR_MAX_LAT values for 16-GT (GTHE3_CHANNEL) in UltraScale device.

Binary Counter (12.0)
 * Version 12.0 (Rev. 4)
 * No changes.

Block Memory Generator (8.2)
 * Version 8.2 (Rev. 1)
 * Updated the GUI tool tip for Byte write enable in the page-1 of block memory generator GUI.

CIC Compiler (4.0)
 * Version 4.0 (Rev. 4)
 * No changes.

CORDIC (6.0)
 * Version 6.0 (Rev. 4)
 * No changes.

CPRI (8.2)
 * Version 8.2 (Rev. 1)
 * Updated to use version 1.3 of the UltraScale GT Wizard.
 * Changes to quad PLL and alignment interfaces to ease core integration in IPI.

Chroma Resampler (4.0)
 * Version 4.0 (Rev. 4)
 * No changes.

Clocking Wizard (5.1)
 * Version 5.1 (Rev. 3)
 * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065.

Color Correction Matrix (6.0)
 * Version 6.0 (Rev. 5)
 * Fix default value GUI bug for CLIP parameter.

Color Filter Array Interpolation (7.0)
 * Version 7.0 (Rev. 4)
 * No changes.

Complex Multiplier (6.0)
 * Version 6.0 (Rev. 5)
 * Removed component statement for DSP48E2, no functional changes.

Convolution Encoder (9.0)
 * Version 9.0 (Rev. 4)
 * No changes.

DDS Compiler (6.0)
 * Version 6.0 (Rev. 5)
 * DDS_Clock_Rate maximum value of 550MHz may restrict designs on new, fast devices. Setting Parameter Entry to Hardware_parameters can be used to work around the restriction.

DSP48 Macro (3.0)
 * Version 3.0 (Rev. 6)
 * Fixed behavior of carrycascout output for fabric-only implementation (use_dsp48=false) when an instruction specifies internal ALUMODE to be 0010 or 0001.

DUC/DDC Compiler (3.0)
 * Version 3.0 (Rev. 4)
 * No changes.

Discrete Fourier Transform (4.0)
 * Version 4.0 (Rev. 4)
 * No changes.

DisplayPort (4.2)
 * Version 4.2 (Rev. 2)
 * Fixed sync_cell instantiation in rx_interrupt module.

Distributed Memory Generator (8.0)
 * Version 8.0 (Rev. 5)
 * Repackaged to improve internal automation, no functional changes.

Divider Generator (5.1)
 * Version 5.1 (Rev. 3)
 * Disabled unnecessary assertions which triggered incorrectly when low latency serial dividers were simulated.  No functional changes.

ECC (2.0)
 * Version 2.0 (Rev. 5)
 * Repackaged to improve internal automation, no functional changes.

Ethernet 1000BASE-X PCS/PMA or SGMII (14.2)
 * Version 14.2 (Rev. 1)
 * gtwizard_ultrascale upgraded to v1_3.
 * Minor constraints modification as per change in tool behavior.
 * Removal and corrections in unused synchronizers in 7-Series transceiver Reset FSM.

Ethernet PHY MII to Reduced MII (2.0)
 * Version 2.0 (Rev. 5)
 * Example design updated to issue reset when clocks are stable.

FIFO Generator (12.0)
 * Version 12.0 (Rev. 1)
 * Repackaged to improve internal automation, no functional changes.

FIR Compiler (7.1)
 * Version 7.1 (Rev. 4)
 * Removed component statement for DSP48E2, no functional changes.
 * Internal change management process enhancements, no functional changes.

Fast Fourier Transform (9.0)
 * Version 9.0 (Rev. 4)
 * No changes.

Fixed Interval Timer (2.0)
 * Version 2.0 (Rev. 4)
 * Removed revision control tags from source code comments, no functional changes.

Floating-point (7.0)
 * Version 7.0 (Rev. 5)
 * Added default values to signals in the Exponential operator to avoid X's being output in behavioral simulation while the pipeline fills and M_AXIS_RESULT_TVALID is Low.  Functionality is unchanged.
 * Removed component statement for DSP48E2, no functional changes.
 * Internal change management process enhancements, no functional changes.

G.709 FEC Encoder/Decoder (2.1)
 * Version 2.1 (Rev. 2)
 * Standardized error reporting for demo testbench across all simulators.

G.975.1 EFEC I.4 Encoder/Decoder (1.0)
 * Version 1.0 (Rev. 5)
 * Changed instantiation of RAMB18SDP to RAMB18E1 to resolve mismatch between behavioral and post-synthesis simulation.

G.975.1 EFEC I.7 Encoder/Decoder (2.0)
 * Version 2.0 (Rev. 5)
 * Repackaged IP to put demo testbench in vhdl-testbench filegroup, no functional changes.

Gamma Correction (7.0)
 * Version 7.0 (Rev. 5)
 * Changed default AXI4-Lite interface enablement from selected to unselected. Existing IP instances are unchanged.

Gmii to Rgmii (3.0)
 * Version 3.0 (Rev. 2)
 * Support for Defense and Automotive grade zynq devices.

High Speed SelectIO Wizard (1.0)
 * Version 1.0 (Rev. 1)
 * CRTL_CLK INTERNAL defeatured.

IBERT 7 Series GTH (3.0)
 * Version 3.0 (Rev. 5)
 * Fixed TIMING DRC violations in IBERT IP and added ASYNC_REG property on register which has double synchronizer in CDC paths.

IBERT 7 Series GTP (3.0)
 * Version 3.0 (Rev. 5)
 * Added new device support for QArtix7 families.
 * Added the package - cs325 fg484.
 * Fixed TIMING DRC violations in IBERT IP and added ASYNC_REG property on register which has double synchronizer in CDC paths.
 * Changed synthesis setting controlset threshold to 100 for 50t, 35t and 100t devices to fix placer issue.

IBERT 7 Series GTX (3.0)
 * Version 3.0 (Rev. 5)
 * Added Device Support for new Zynq Automotive and Defense grade parts.
 * Fixed TIMING DRC violations in IBERT IP and added ASYNC_REG property on register which has double synchronizer in CDC paths.

IBERT 7 Series GTZ (3.1)
 * Version 3.1 (Rev. 3)
 * Internal HDL change, no functional changes.
 * Fixed TIMING DRC violations in IBERT IP and added ASYNC_REG property on register which has double synchronizer in CDC paths.

IBERT Ultrascale GTH (1.0)
 * Version 1.0 (Rev. 1)
 * Added New Device Support.
 * Updated GTWizard Subcore reference.

ILA (Integrated Logic Analyzer) (4.0)
 * Version 4.0 (Rev. 1)
 * Fixed TIMING DRC violations, added ASYNC_REG property on the register which has double synchronizer for CDC paths.
 * Fixed re-execution of First state when ila is used in advanced trigger mode.
 * Reduced number of unused ports visible to users for AXI mode when AXI4LITE protocol is selected.

IOModule (2.2)
 * Version 2.2 (Rev. 2)
 * Removed revision control tags from source code comments, no functional changes.

Image Enhancement (8.0)
 * Version 8.0 (Rev. 4)
 * Changing the number of columns via the AXI4-Lite interface now updates correctly within the core.

Interleaver/De-interleaver (8.0)
 * Version 8.0 (Rev. 4)
 * No changes

JESD204 (5.2)
 * Version 5.2 (Rev. 1)
 * ZYNQ-7000 XC7Z015 support added (check DS190 for the maximum number of GTPs available in each part/package).
 * Updated to use version 1.3 of the UltraScale GT Wizard.
 * Updated to use version 3.3 of the 7-Series GT Wizard.
 * Improved GUI speed and responsiveness, no functional changes.
 * Fixed auto upgrade issue (Xilinx Answer 60386).
 * Fixed UltraScale GT Wrapper DRPCLK clock connections for multi-lane core designs (Xilinx Answer 60387).
 * Fixed an issue on the GUI symbol where the gt_dmonitorout ports did not appear in the transcevier_debug bus interfaces when targeting the GTXE2 transceivers.
 * Fixed an issue on the GUI symbol where the gt_drpaddr ports showed a width of 16 in the DRP Buses.

JTAG to AXI Master (1.0)
 * Version 1.0 (Rev. 3)
 * Added jtag_axi_v1_0_jtag_axi_sim.v file as simulation source.

LMB BRAM Controller (4.0)
 * Version 4.0 (Rev. 4)
 * Removed revision control tags from source code comments, no functional changes.

LTE DL Channel Encoder (3.0)
 * Version 3.0 (Rev. 5)
 * Product Brief renamed from xmp to pb.

LTE Fast Fourier Transform (2.0)
 * Version 2.0 (Rev. 5)
 * Product Brief renamed from xmp to pb.

LTE PUCCH Receiver (2.0)
 * Version 2.0 (Rev. 5)
 * Product Brief renamed from xmp to pb.

LTE RACH Detector (2.0)
 * Version 2.0 (Rev. 5)
 * Product Brief renamed from xmp to pb.

LTE UL Channel Decoder (4.0)
 * Version 4.0 (Rev. 5)
 * Internal change management process enhancements, no functional changes.

Local Memory Bus (LMB) 1.0 (3.0)
 * Version 3.0 (Rev. 4)
 * Removed revision control tags from source code comments, no functional changes.

Mailbox (2.1)
 * Version 2.1 (Rev. 1)
 * Removed revision control tags from source code comments, no functional changes.

Memory Interface Generator (MIG 7 Series) (2.1)
 * Version 2.1
 * DDR3 clocking and read path calibration updates. Refer to Answer Record 60687 for details.
 * Addition of Artix-7Q(xq7a50t-cs325,xq7a50t-fg484) and XAZynq (xa7z030-fbg484) devices.

Memory Interface Generator (MIG) (5.0)
 * Version 5.0 (Rev. 1)
 * Support of UDIMM and SODIMM for DDR3 and DDR4 interfaces.
 * RLDRAM3 X18 memory device Support.
 * QDRIIP BL2 X36 memory device Support.
 * Resolved issue with GUI allowing deselection of DDR4 Internal Vref. See (Xilinx Answer 60322) for details.
 * Resolved issue with dbg_clk connection for DDR3/DDR4 designs.  See for (Xilinx Answer 59948) details.

MicroBlaze (9.3)
 * Version 9.3 (Rev. 1)
 * Internal change management process enhancements, no functional changes.

MicroBlaze Debug Module (MDM) (3.1)
 * Version 3.1 (Rev. 1)
 * Removed revision control tags from source code comments, no functional changes.

MicroBlaze MCS (2.2)
 * Version 2.2 (Rev. 1)
 * Removed revision control tags from source code comments, no functional changes.

Multiplier (12.0)
 * Version 12.0 (Rev. 5)
 * Removed component statement for DSP48E2, no functional changes.

Multiply Adder (3.0)
 * Version 3.0 (Rev. 4)
 * No changes.

Mutex (2.1)
 * Version 2.1 (Rev. 1)
 * Removed revision control tags from source code comments, no functional changes.

Peak Cancellation Crest Factor Reduction (5.0)
 * Version 5.0 (Rev. 2)
 * The set_property used in constraint file for converting all the BRAMs from READ_FIRST to WRITE_FIRST mode has been updated such that it works both for 7-series as well as UltraScale devices.
 * Repackaged IP to put demo testbench in vhdl-testbench filegroup, no functional changes.

Processor System Reset (5.0)
 * Version 5.0 (Rev. 5)
 * Enhanced support for IP Integrator.
 * Board flow related updates, no functional changes.

QSGMII (3.2)
 * Version 3.2 (Rev. 1)
 * Uprev of UltraScale wizard to version 1.3.

RAM-based Shift Register (12.0)
 * Version 12.0 (Rev. 4)
 * No changes

RGB to YCrCb Color-Space Converter (7.1)
 * Version 7.1 (Rev. 2)
 * No changes

RXAUI (4.2)
 * Version 4.2 (Rev. 1)
 * Added support for Z-7015 devices.
 * Updated to use the latest GT UltraScale Wizard.
 * Fixed an issue on the GUI symbol where the gt_dmonitorout ports did not appear in the transcevier_debug bus interfaces when targeting the GTHE2 and GTXE2 transceivers.

Reed-Solomon Decoder (9.0)
 * Version 9.0 (Rev. 5)
 * Modified demonstration testbench to ensure that the expected number of errors are in the data block while using puncture patterns. No functional changes to the synthesis HDL.

Reed-Solomon Encoder (9.0)
 * Version 9.0 (Rev. 4)
 * No changes

S/PDIF (2.0)
 * Version 2.0 (Rev. 5)
 * Updated Example design XDC for timing DRC, no functional changes.

SMPTE 2022-1/2 Video over IP Receiver (1.0)
 * Version 1.0 (Rev. 3)
 * Fix AXI-MM read error that caused payload corruption when rvalid is deasserted.

SMPTE 2022-1/2 Video over IP Transmitter (1.0)
 * Version 1.0 (Rev. 3)
 * Fix for secondary VLAN tag value stuck at zero
 * Fix for core not generating Non Block Align FEC when bit0 of FEC_CONFIG register set to 1.
 * Changed the mechanism of how the core handles the push back from AXIS MAC interface. Push back at either Primary or Secondary link propagates to the Transport stream input interface of the system.

SMPTE SD/HD/3G-SDI (3.0)
 * Version 3.0 (Rev. 1)
 * No changes

SMPTE2022-5/6 Video over IP Receiver (3.0)
 * Version 3.0 (Rev. 5)
 * Fix AXI-MM read error that caused payload corruption when rvalid is deasserted.
 * Added Destination IP for filtering channel and increase the firewall_sel bits from 2 to 3 (register 0x110 bit2).

SMPTE2022-5/6 Video over IP Transmitter (3.0)
 * Version 3.0 (Rev. 4)
 * No changes.

SPI-4.2 (13.0)
 * Version 13.0 (Rev. 4)
 * No changes.

SelectIO Interface Wizard (5.1)
 * Version 5.1 (Rev. 2)
 * Repackaged to improve internal automation, no functional changes.
 * Updated example design for MMCME2 COMPENSATION = BUF_IN.

Serial RapidIO Gen2 (3.1)
 * Version 3.1 (Rev. 2)
 * Fixed the VHDL netlist failure issue for sys_rst port due to pull up settings in the XDC files dedicated for Artix7, Kintex7, Virtex7 devices, no functional changes.
 * Fixed critical warning issue due to incorrect create clock constraints mentioned in the ooc.xdc file, no functional changes.

Soft Error Mitigation (4.1)
 * Version 4.1 (Rev. 1)
 * Resolved (Xilinx Answer 60056). Makedata.tcl is no longer incorrectly displayed as a simulation source file.
 * Resolved AR (Xilinx Answer 60058). Corrected the listed support of xc7a75t, xc7z030, and xc7z015 from Pre-Production to Production.
 * This version of the IP does not yet support new device xq7a50t.

System Cache (3.0)
 * Version 3.0 (Rev. 5)
 * Changed code to support third-party simulators, no functional changes.
 * Removed revision control tags from source code comments, no functional changes.

System Management Wizard (1.1)
 * Version 1.1
 * Added support for UltraScale SSI devices
 * Added optional port sysmon_slave_sel, present for DRP interface in SSI devices.
 * Increased size of input s_axi_araddr and s_axi_awaddr from 11 to 13. When upgrading from previously released core, please update your design to instantiate this correctly.
 * When upgrading a design with External Multiplexer mode enabled from previously released core , vauxp/vauxn ports will not be available other than the selected Mux Channel and users will need to update their design.

Ten Gigabit Ethernet MAC (13.1)
 * Version 13.1 (Rev. 1)
 * Fix for corner case usage of Priority Flow Control on transmit when Oneshot and XON/XOFF are mixed on the same priority.

Ten Gigabit Ethernet PCS/PMA (10GBASE-R/KR) (4.1)
 * Version 4.1 (Rev. 2)
 * Updated to use the latest GT UltraScale Wizard
 * Fixed an issue on the GUI symbol where the port gt0_dmonitorout did not appear in the transceiver_debug bus interface when targeting the GTHE2 transceiver.
 * Fixed an issue in the core GUI customization code which caused an error to appear in the Vivado Messages window when the GUI was first opened.

Test Pattern Generator (6.0)
 * Version 6.0 (Rev. 1)
 * Fixed a problem with the core timing out after a fixed duration, no functional changes.

Timer Sync 1588 (1.2)
 * Version 1.2
 * No changes.

Tri Mode Ethernet MAC (8.2)
 * Version 8.2 (Rev. 1)
 * Updated false path constraint for the path - bus2ip_addr_int_reg to gtx_clk, in <compname>_clocks XDC file, to fix the critical warning for the case in which the source register, bus2ip_addr_int_reg, was getting renamed to bus2ip_int_reg_rep, post-synthesis.

UltraScale FPGAs Transceivers Wizard (1.3)
 * Version 1.3
 * Added several new transceiver configuration preset options.
 * Enabled synthesis and implementation of configurations utilizing GTY transceivers.
 * Refined timing constraints and their locations in XDC files to reduce warnings and redundancy.
 * Added a CDR lock timeout counter to the reset controller helper block to avoid the possibility of the RX data path reset sequence hanging due to no RXCDRLOCK assertion.
 * Improved performance of GTH transceivers via parameter updates.
 * Fixed a wiring bug in the receiver module of the user data width sizing helper block that affected only GTY transceivers configured to use the 160-bit RX user data width.
 * Fixed a small number of discrepancies between frequency/rate limits imposed by the Wizard GUI and some published UltraScale Architecture Data Sheet values.
 * Added logic to the example design which demonstrates proper reset stimulus of the buffer bypass controller helper blocks.

UltraScale FPGA Gen3 Integrated Block for PCI Express (3.0)
 * Version 3.0 (Rev. 1)
 * Fixed timing violations with non x0y0 pcie blocks.
 * Added support for KintexU devices xcku100 and xcku115.
 * Added support for VirtexU devices xcvu080 and xcvu125.
 * Disabled the parameters pf0_rbar_capability and pf1_rbar_capability.

VIO (Virtual Input/Output) (3.0)
 * Version 3.0 (Rev. 3)
 * simplified constraint definition.
 * Improved Distributed RAM usage.

Video Deinterlacer (4.0)
 * Version 4.0 (Rev. 5)
 * Fixed configuration GUI issue recorded in (Xilinx Answer 60171).

Video In to AXI4-Stream (3.0)
 * Version 3.0 (Rev. 4)
 * No changes

Video On Screen Display (6.0)
 * Version 6.0 (Rev. 5)
 * Added new TCL command support in module xdc file.

Video Scaler (8.1)
 * Version 8.1 (Rev. 3)
 * No changes

Video Timing Controller (6.1)
 * Version 6.1 (Rev. 2)
 * Internal change management process enhancements, no functional changes.

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (3.0)
 * Version 3.0 (Rev. 2)
 * Added new module _force_adapt.v for compliance fix.

Viterbi Decoder (9.0)
 * Version 9.0 (Rev. 5)
 * Internal change management process enhancements, no functional changes.

XADC Wizard (3.0)
 * Version 3.0 (Rev. 4)
 * Fixed issue with VCCBRAM channel enablement in INIT_48 for sequencer mode.

XAUI (12.1)
 * Version 12.1 (Rev. 2)
 * Updated to use the latest GT UltraScale Wizard.
 * Fixed an issue on the GUI symbol where the gt_dmonitorout ports did not appear in the transcevier_debug bus interfaces when targeting the GTHE2 and GTXE2 transceivers.

YCrCb to RGB Color-Space Converter (7.1)
 * Version 7.1 (Rev. 2)
 * No changes.

ZYNQ7 Processing System (5.4)
 * Version 5.4 (Rev. 1)
 * Add the polarity feature for reset (USB, I2C and Ethernet) pins.
 * Add the IP type is processor.
 * Fixed LPDDR2 hang Issue.

ZYNQ7 Processing System BFM (2.0)
 * Version 2.0 (Rev. 3)
 * add a new API that helps do a backdoor read to the memories(OCM and DDR).

interrupt_controller (3.0)
 * Version 3.0 (Rev. 1)
 * No changes.

proc_common (4.0)
 * Version 4.0 (Rev. 1)
 * CDC module updated to use FDR to do away with DONT_TOUCH attribute.
 * No functional changes.

AR# 61087
Date 06/23/2014
Status Archive
Type Release Notes