When the sys_rst signal is driven from an internal register within the user design and is run on a clock that is related to the clk_ref, it can be difficult or impossible to meet timing.
Is the failing path on the FDPE "PRE" pin for sys_rst (see below figure) a true violation?
Sys_rst is a fully asynchronous reset pin.
Inside the MIG core, the reset is synchronized to the internal clk_ref to create a synchronous reset.
Therefore, it is asserted asynchronously and deasserted synchronously.
Because of this design, it is perfectly safe to put a set_false_path constraint on the sys_rst pin.