UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61154

v3.1 - 7 Series FPGAs Transceivers Wizard - simulation fails if both LPM mode and Near-end PMA Loopback are selected at the same time.

Description

Simulation will fail if both LPM mode and Near-end PMA Loopback are selected at the same time.

When LOOPBACK is set to 3'b010 and RXLPMEN is 1'b1, RXDATA will be "0" in simulation.


Solution

RXDATA is correct in DFE mode or in Near-end PCS mode.

The workaround is to use Near-end PCS mode instead of Near-end PMA mode in simulation.
 
This issue is scheduled to be fixed in a future release.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

This is an issues with latency of the core.
AR# 61154
Date Created 06/16/2014
Last Updated 06/24/2014
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Virtex-7
IP
  • 7 Series FPGAs Transceivers Wizard