This error has been seen in the following situations.
- When an Aurora 64B66B IP core is used in a block design and some of the clock-ports are specifying their FREQ_HZ as double (for example sync_clk and user_clk).
While writing the OOC XDC file during HDL generation, Vivado is doing a bad lexical cast while interpreting this data.
- In cases where the AXI
Ethernet and AXI 10G Ethernet have not specified CONFIG.FREQ_HZ and
CONFIG.PHASE parameters for their clock-output pins in 2014.2.
lexical_cast problem will happen during post parameter-propagation DRC checks (validate_bd_design) when running clock-reset synchronization DRC.
This happens because the clock output ports frequency could not
be found by looking only at hierarchy boundary.
runs parameter propagation during "generate_target" and "Create HDL wrapper" so the error will occur when running
these tasks as well.
This issue will be fixed in Vivado release 2014.3.
A patch has been created to resolve this error in Vivado 2014.2.
To install this patch download the attached zip file for the desired operating system and follow the instructions provided in the readme file contained in the archive.