The Constraints Editor is not locating all clock signals in my design. Generally, the Constraints Editor finds clock nets and traces them back to their source. At the source, they are named and made available for period constraints. Net names along the path of that clock are displayed with the source signal name.
Specifically, derived clocks do not appear; a clock signal that is derived from multiple clock signals through a MUX or other such function does not appear. Even if a BUFG is applied to that signal, it is not visible.
Using the UCF file, you can name any clock net, and you can add a period constraint (this is limited to the Constraints Editor, not to the constraint itself). You can manually add a clock signal that is not available in the Constraints Editor to the UCF file and apply the constraint.
For details on adding period constraints, refer to the software manuals at: