The MDIO ready signal is also
available in register 0x504 bit 7.
Instead of polling MDIO ready in register 0x50C and then reading the MDIO read data at the same time, the following steps could be used to work around this issue:
This tactical patch contains the v8.2 rev2 tactical patch which fixes this issue:
Fixes issue in which AXI4-Lite register 0x50C can indicate MDIOREADY high without updating MDIO RX Data if the AXI4-Lite read happens immediately after the completion of the MDIO read cycle.
This Tactical Patch is compatible with Vivado 2014.2.
In addition to this readme, the ar61328_tr_mode_eth_mac_v8_2_Rev2_preliminary_patchrev1.zip file contains the Tri-Mode Ethernet MAC v8.2(Rev. 2) core
For further information on finding the Xilinx install and using the environment variable, see (Xilinx Answer 11630).
For further information on using the MYVIVADO environment variable, see (Xilinx Answer 53821).
Note: You might need to have a system administrator install the Patch if you do not have write permissions to the Xilinx Install directory, or cannot use the MYVIVADO option.
Who to Contact if you have problems?
Xilinx Technical Support
|Name||File Size||File Type|