UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 61341: 14.6 Sysgen - A Fatal Internal Error sometimes occurs when generating a Netlist

AR# 61341

14.6 Sysgen - A Fatal Internal Error sometimes occurs when generating a Netlist

Description

While generating a netlist, a "Fatal Internal Error" occurs, reported by a simple model (eg constant).  

This issue does not occur every time.

After the error is received I cannot generate a netlist or run Hardware Cosim for a very simple design.

Restarting Matlab will sometimes fix the issue.

What is the cause of this problem?

Solution

This issue only affects 64bit Sysgen.

Sysgen encounters problems with the license file when it is located under C:\.Xilinx.
 
It can be fixed by leaving C:\.Xilinx empty, saving Xilinx.lic to a different location (for example C:\Xilinx_license\Xilinx.lic), and pointing to it by using the environment variable XILINXD_LICENSE_FILE

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44617 System Generator for DSP v14.7 - Creating a netlist results in an error, "An internal error occurred in the Xilinx Blockset Library" N/A N/A
58034 ISE Design Suite 14, DSP Tools (System Generator for DSP) (14.7) - Release Notes and Known Issues N/A N/A
AR# 61341
Date 07/14/2014
Status Active
Type Known Issues
Tools
  • System Generator for DSP - 14.6
  • System Generator for DSP - 14.7