UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61378

Aurora 8B10B v10.1 or earlier - WARNING: [Synth 8-327] inferring latch for variable 'storage_31_reg'

Description

With Aurora 8B10B v10.1, latches can be inferred for the variable 'storage_31_reg'.

The Following warning message is received:
.

WARNING: [Synth 8-327] inferring latch for variable 'storage_31_reg' [.*/my_ip_example/my_ip_example.srcs/sources_1/ip/my_ip/my_ip/src/my_ip_storage_switch_control.vhd:1293]


This issue applies to VHDL cores only.

This answer record provides the updates required to avoid this behavior.

Solution

The "storage_31_reg" signal is not initialized while declaring it.
 
Please initialize this signal to '0' as shown below to avoid latches being inferred.
signal storage_31 : std_logic_vector(0 to 5) := "000000";

Revision History:
08/04/2014 - Initial Release
AR# 61378
Date Created 07/03/2014
Last Updated 08/06/2014
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • Aurora 8B/10B