We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61391

Vivado - PROHIBIT contraints affect report_utilization


When opening a Vivado project and running report_utilization on the synthesized design, the available logic is less than expected.
For example, on a xc70tfbg484, the following is expected:
SLICE LUT: 41000
SLICE REG: 82000
The following is what is actually shown from report_utilization:
SLICE LUT: 40940
SLICE REG: 81880;
Why is this the case?


The PROHIBIT constraints reduce the available logic shown in the utilization report.

Please check your XDC constraints for constraints of this type.
For example: 
set_property PROHIBIT [true/false] [get_sites SLICE_X3Y122]
AR# 61391
Date 09/29/2014
Status Active
Type General Article
  • Vivado Design Suite