We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61428

MIG UltraScale DDR4/DDR3 – What is the recommended flow for creating a PHY Only design?


Version Found: MIG v6.0
Version Resolved: See (Xilinx Answer 58435)

MIG UltraScale currently does not deliver a PHY-Only solution where the controller and user interface are removed, allowing users to integrate custom controllers. 

This support will be provided through the MIG GUI starting with Vivado 2014.4. 

When using MIG v6.0 available with Vivado 2014.3, this Answer Record can be followed to manually create a PHY only solution. 

The Answer Record provides manual steps to modify the full MIG UltraScale DDR4/3 IP to remove the controller and user interface leaving only the PHY and calibration logic.  


1.   Create the MIG IP in Vivado for the required configuration.
2.   Generate all targets but turn-off OOC while generating.
This will generate all the required files (RTL, others) but not run synthesis to generate a DCP for the IP.


3.   Next a set of RTL files need to be updated/added/removed.
To make rtl edits, please use an external editor. Vivado will not allow files to be edited.

4.   In the generated design, edit the mig_v5_0_ddr4_mem_intfc.sv file to remove the memory controller (mc) and user interface (UI): (please refer to attached file for an example)

  • Comment out the mig_v5_0_ddr_mc and mig_v5_0_ddr_ui instances.
  • For all signals that are connected to the ports of the above mc and ui instances, perform the following:
    • All top-level ports which connect to the *_mc or *_ui instances --> comment-out/remove
    • All signals/wires which connect the *_mc and *_ui instances together --> comment-out/remove
    • Signals that are driven out of the *_mc and *_ui instances and connect as inputs of mig_v5_0_ddr4_phy --> Make these signals top level input ports.
      • All top-level ports which connect to the *_phy and either the *_mc or *_ui instances need to be retained (e.g. div_clk)
      • These signals may be renamed as: phy_<original_name>, to be in line with the modified connectivity.
      • Some of the ports of the *_phy instance do not need to be brought to the top-level as they are not used at the top.
        These signals are: bank, cmd, col, group, hiPri, row, size, useAdr    .

5.   In the generated design, edit the mig_0_mig.sv file: (please refer to attached as an example)

  • Update the instantiation of the mig_v5_0_ddr4_mem_intfc to match the updated port-list.
  • Bring out the PHY-ports to the top-level.

6.   Edit the mig_0.sv file: (please refer to attached as an example)

  • Update the instantiation of the mig_v5_0_ddr4_mem_intfc to match the updated port-list.
  • Bring out the PHY-ports to the top-level.

7.   After modifying the files, do not re-customize MIG. If MIG is re-customized, all of the updated files in the above steps will be over-written.

  • The .xci file exists in the project to ensure a smooth implementation of ELF association used for the calibration code.
    Please do not double-click, make any changes, or save the .xci.

8.   Add a top level wrapper.  You can use the attached example_top.sv and example_tb_phy.sv files as an example.

  • The parameters of these wrappers change for each specific MIG configuration.
    The attached example_top and example_tb_phy files need to be updated for the specific configuration or else used as examples only.

9.   After making these changes, the design hierarchy should look like the following:

10. A top-level constraint file is needed to provide physical location constraints for the DDR interface and other diagnostic signals need to be provided.

  • A convenient way to create this XDC file is to re-use the mig_0.xdc file from the generated MIG IP which can be found at this location:
    • <project_name>/<project_name>.srcs/sources_1/ip/mig_0/par/mig_0.xdc
    • For any port names in the copied XDC file which are 1-bit, but are referenced with an "[0]" index, please remove the "[0]" index from those signal names.
      This is because at the top-level all of these ports are defined as scalar.
      • This may not always be the case, so the user needs to ensure that they review all "Critical Warnings" generated by Vivado during implementation.
    • Add PACKAGE_PIN/IOSTANDARD constraints for the diagnostic signals  "c0_init_calib_complete" and "c0_data_compare_error".
  • A sample XDC file can be found attached.

11.  Run synthesis, implementation and generate bitstream

Note:  There may be a Critical Warning related to pblock constraint which can be ignored.
Below is an example:

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 61428
Date 03/23/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale
Page Bookmarked