We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61456

2014.2 Vivado HLS - Tool does not recognize mult-adder for one DSP and resource estimation is not consistent with RTL evaluation.


In the sample code below, I would expect it to be packed into one DSP, with OP MODE: C+A*B.

#include "ap_cint.h"
int48 ybd(int18 in1, int16 in2, int48 in3){
 int48 sum;
 return sum;

However, HLS C synthesis reports 1 DSP + 49 LUTs.

RTL evaluation reports only 1 DSP.


By default, HLS will convert multiplication in1*in2 to a multiplier with 32 bits output, according to the C compiler's rule.

You would need to use explicit cast as below to get the expected result:


AR# 61456
Date 03/05/2015
Status Active
Type General Article
  • Vivado Design Suite - 2014.2
Page Bookmarked