This example design is used to test for a Zynq L2-Cache parity error.
Data will be corrupted, and the parity error will be reported by an SLVERR and an interrupt.
The following behavior is expected to be processed
An L2 Cache parity error can be generated with the following steps:
The attached C code for the same is for reference.The software was generated by Vivado 2014.2 and tested on a ZC702 production board.
|PS Features||L2 cache, GIC|
|Xilinx Tools Version||Vivado 2014.2|
|Name||File Size||File Type|
|Boards & Kits||