This example design is used to test for a Zynq L2-Cache parity error.
Data will be corrupted, and the parity error will be reported by an SLVERR and an interrupt.
The following behavior is expected to be processed
An L2 Cache parity error can be generated with the following steps:
The attached C code for the same is for reference.
The software was generated by Vivado 2014.2 and tested on a ZC702 production board.
Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.
A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.
It is the users responsibility to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill their needs.
Limited support is provided by Xilinx on these Example Designs.
|PS Features||L2 cache, GIC|
|Xilinx Tools Version||Vivado 2014.2|
|Name||File Size||File Type|
|Boards & Kits||