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AR# 61457

Zynq-7000 Example design – L2 Cache Parity Error Test (interrupt and AXI SLVERR response)


This example design is used to test for a Zynq L2-Cache parity error. 

Data will be corrupted, and the parity error will be reported by an SLVERR and an interrupt.

The following behavior is expected to be processed

  • an IRQ interrupt (IRQ No.34 for L2 cache) - PARRT : Parity Error on L2 Tag RAM (Read)
  • a Data abort exception for an SLVERR response.


An L2 Cache parity error can be generated with the following steps:

  1. Disable L2 cache
  2. Disable the parity
  3. Enable L2 cache //
  4. Write data
  5. Disable L2 cache
  6. Enable parity
  7. Enable L2 cache
  8. Read data


The attached C code for the same is for reference. 

The software was generated by Vivado 2014.2 and tested on a ZC702 production board. 

Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.

A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.

It is the users responsibility to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill their needs.

Limited support is provided by Xilinx on these Example Designs. 

Implementation Details
Design Type PS
SW Type Standalone
CPUs Single CPU
PS Features L2 cache, GIC
Boards/Tools ZC702
Xilinx Tools Version Vivado 2014.2
Other details  
Files Provided
L2CacheParityError.zip   SW program



Step by Step Instructions
  1. In SDK 2014.2, generate a zc702 empty application and import the software.
  2. Set up the terminal.
  3. Run the application.
Expected Results

Interrupt/Data Abort information will be printed as below







Associated Attachments

Name File Size File Type
L2CacheParityError.zip 6 KB ZIP
AR# 61457
Date 10/27/2017
Status Active
Type General Article
  • Zynq-7000
  • Vivado Design Suite - 2014.2
Boards & Kits
  • Zynq-7000 SoC ZC702 Evaluation Kit
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