Starting with version 3.3 of the 7 Series FPGAs Transceivers Wizard which ships in Vivado 2014.2, the low level GTX wrapper generated by the wizard contains some added logic.
This logic keeps the CPLL in power down mode until the reference clock supplied to the CPLL has had time to propagate through the reference clock distribution and into the CPLL.
This prevents spikes on the CPLL power rail caused by the CPLL being powered on when the reference clock hasn't yet reached the CPLL.
There is about a 1ms propagation time for the reference to reach the CPLL.
The GT wizard always generates this code based on the assumption that gtrefclk0_in is used as the CPLL reference clock.
When another reference clock is actually being supplied to the CPLL, this will defeat the purpose of the code.
If another reference clock is being used and gtrefclk0_in does not have a valid clock applied to it, the CPLL will remain powered down indefinitely.
After the GTX wrapper has been generated as described in the text of XAPP 592, the lowest level GTX wrapper (the wrapper used by SDI), must be edited manually to use the proper reference clock in this code segment.
Both SDI demos that are supplied here use gtrefclk1_in as the CPLL reference clock.
The k7gtx_sdi_wrapper_gt.v file supplied for these demos has already been edited to use gtrefclk1_in in this CPLL power down code.
Please see the XAPP592 readme.txt file for more details.