After running implementation for my Block Design (BD) which contains the Zync Processing System with DDR3L interface enabled, I notice that the DDR_ck_n and DDR_ck_p IO ports do not have the correct IOSTANDARD applied.
They default to LVCMOS18 which is not correct for a DDR3L (low power DDR3).
Is this a known issue or expected behavior?
This is a known issue which is present in Vivado 2014.2.
To work around this problem, please manually constrain the IOSTANDARD in your project XDC file as follows:
This issue is fixed starting in Vivado 2014.3.