Version Found: v5.0 Rev1
Version Resolved: See (Xilinx Answer 58435)
Cypress QDRII+ memory models give erroneous data errors as a result of the data_out output being driven by two drivers.
The simulation can also fail as a result of the memory model not returning data edge aligned with the CQ/CQ# clock to emulate noise.
Because MIG UltraScale does not support full calibration during behavioral simulations, the misaligned data and clock will not be aligned properly and might still cause data failures.
Simulation can fail with the following message:
To work around the issue, ensure that the driving events do not occur at the same time and also that the data is received edge aligned with the clock.
This can be done by changing the "tcqd" parameter in the Verilog memory model from #0.15 to #0.0.
For more information contact Cypress directly, or refer to the Cypress Knowledge Base Article on this topic:
|06/08/2017||Added simulation error message|