AR# 61555


UltraScale/UltraScale+ QDRII+ IP - Multi-driver issue in Cypress memory model causes data errors in simulation


Version Found: v5.0 Rev1

Version Resolved: See (Xilinx Answer 69038)

Cypress QDRII+ memory models give erroneous data errors as a result of the data_out output being driven by two drivers.

The simulation can also fail as a result of the memory model not returning data edge aligned with the CQ/CQ# clock to emulate noise.

Because MIG UltraScale does not support full calibration during behavioral simulations, the misaligned data and clock will not be aligned properly and might still cause data failures.

Simulation can fail with the following message:

TEST FAILED: DATA ERRORINFO: Timing violations reported by memory model could be incorrect due to model issue.
Please check the violations and contact Cypress for further assistance.
$finish called at time : 2513877 ps : File "/vob/uea/prog_parts/interstellar/karna/my_folder2/qdriip_0_ex/imports/" Line 462


To work around the issue, ensure that the driving events do not occur at the same time and also that the data is received edge aligned with the clock.

This can be done by changing the "tcqd" parameter in the Verilog memory model from #0.15 to #0.0.

For example:

`define tcqd #0.15
`define tcqd #0.0

For more information contact Cypress directly, or refer to the Cypress Knowledge Base Article on this topic:

Revision History:

06/08/2017Added simulation error message
07/20/2014Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69038 UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues N/A N/A
AR# 61555
Date 01/17/2018
Status Active
Type Known Issues
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