|FPGA Speed Grade||Maximum Supported DDR3 Rate|
There is currently only one TwinDie part included in the MIG GUI list, MT41K512M8THD-15E.
However MIG currently limits this device to 1066 Mb/s operation for all speed grades.
In order to target a TwinDie component at 1333 Mb/s, top level RTL parameters will need to be modified.
Below is a list of clocking related parameters that need to change when increasing from 1066 Mb/s to 1333 Mb/s (when the input sys_clk period is kept at 1875 ps):
Above 1066 Mb/s operation, the following IODELAY parameters must also be enabled:
By default Vivado generates a .dcp synthesized checkpoint file for each IP when the output products are generated for that core.
Since the underlying MIG RTL needs to be modified, there are a few steps that need to be followed in order to make these edits and properly regenerate the out-of-context synthesis run for MIG:
1. Select the MIG .xci file in the GUI, go to properties and uncheck IS_MANAGED.
2. Right click the .xci, go to IP Hierarchy -> Show IP Hierarchy.
3. Double click on <core_name>_mig.v and <core_name>_sim.v under the .xci to edit the top level parameters.
4. Modify the parameters above and save the files.
5. Under the Design Runs tab at the bottom, right click on <core_name>_synth_1 and click "Reset Runs"
6. Now when you implement the design, the out-of-context synthesis run for MIG will be re-run and an updated .dcp file will be generated.
If a scripted flow is used instead of the GUI, the Verilog files can be modified in a text editor and then the MIG out-of-context synthesis run can be re-run with a command similar to this:
reset_run mig_7series_0_synth_1 launch_runs mig_7series_0_synth_1
07/30/2014 - Initial Release