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PCIe Link training and stability issues make up the vast majority of the issues in interlink connectivity.
This document describes the use case for debugging these issues with the integrated tools in the Xilinx Vivado Design Suite.
This document will be focused on the use of Vivado ILA for debug by capturing link training debug signals in the 7 Series Integrated Block for PCIe IP core, and is also applicable to the AXI Memory Mapped PCIe Bridge core when it is used on a 7 Series part.
The document does not go into detail on the background of link training issues.
For detailed information on debugging link training issues in the 7 Series Integrated Block for PCI Express core, refer to (Xilinx Answer 56616).
|Name||File Size||File Type|
|Vivado ILA Usage Guide for 7 Series Integrated Block for PCI Express||2 MB|