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AR# 61598

Design Advisory Master Answer Record for Kintex UltraScale FPGA

Description

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the Kintex UltraScale FPGA and related issues which impact Kintex UltraScale FPGA designs.

Solution

Design Advisory Alerted on June 19th, 2017

06/13/2017(Xilinx Answer 69152)Design Advisory 2017.1 Tactical Patch for Vivado bi-directional logic issue using component mode primitives (IOBUF usage with IDDRE1, ISERDESE3, ODDRE1, OSERDESE3, or FDCE/FDPE/FDRE/FDSE with IOB=TRUE)

Design Advisories Alerted on April 17th, 2017

04/17/2017(Xilinx Answer 69034)Design Advisory for 7 Series, UltraScale and UltraScale+, all versions of Vivado prior to 2016.3 failed to include Flight time delays for differential I/O Standards.


Design Advisories Alerted on April 10th, 2017

04/10/2017(Xilinx Answer 68832)Design Advisory for UltraScale FPGA, UltraScale+ FPGA, and Zynq UltraScale+ MPSoC eFUSE Programming with Vivado 2016.4 (and earlier)


Design Advisory Alerted on December 26th, 2016

12/26/2016(Xilinx Answer 68169)Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs - New minimum production speed specification version (Speed File) required for all designs

Design Advisory Alerted on December 19th, 2016

12/19/2016(Xilinx Answer 67645)Design Advisory for 7 Series and UltraScale Architecture FPGA configuration fallback and POST_CRC limitation

Design Advisories Alerted on November 1st, 2016

11/01/2016(Xilinx Answer 68006)Design Advisory for Xilinx Design Tools (Vivado, SDAccel, SDSoC) 2016.1 and 2016.2 write_bitstream - Multi-threading might cause configuration memory cells to be set incorrectly

 

 

Design Advisories Alerted on December 21st, 2015

12/21/2015(Xilinx Answer 65792)Design Advisory for UltraScale RSA Authentication - UltraScale devices that use RSA authentication will fail bitstream authentication when smaller configuration interface widths are used.

 

Design Advisories Alerted on Nov 30, 2015

11/30/2015(Xilinx Answer 65998)Design Advisory - System Monitor and PCI Express: I2C_SDA, I2C_SCL, PERSTN0 or PERSTN1 I/O pins have lower than expected Pin voltage levels

Design Advisories Alerted on Oct 19, 2015

10/19/2015(Xilinx Answer 65710)Design Advisory for Kintex UltraScale Speed Files - -3 speed files incorrectly released for KU095

Design Advisories Alerted on July 06, 2015

07/06/2015(Xilinx Answer 64838)Design Advisory for UltraScale FPGA Transceivers Wizard: GTH Production Updates in Vivado 2015.2

 

Design Advisories Alerted on May 04, 2015


05/04/2015(Xilinx Answer 64347)Design Advisory for UltraScale Speed Specification - 2015.1 Production Speed Specification Changes

 

Design Advisories Alerted on March 02, 2015


03/09/2015(Xilinx Answer 63698)Design Advisory for UltraScale Kintex FPGA Speed Files - Possible Hold Violation on dedicated SRL - SRL paths with CFGLUT5

Design Advisories Alerted on December 01, 2014

 


12/01/2014 (Xilinx Answer 62870)Design Advisory for package changes for Virtex UltraScale devices and Kintex UltraScale devices

 

Design Advisories Alerted on November 10, 2014


11/10/2014(Xilinx Answer 62631)Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 series and UltraScale FPGA


Design Advisories Alerted on October 13, 2014

10/13/2014(Xilinx Answer 62157)Design Advisory for MIG UltraScale QDRII+ - pinout DRC violations not caught in I/O Planner

Design Advisories Alerted on July 28, 2014

04/28/2014(Xilinx Answer 61611)Design Advisory for Kintex UltraScale ASCII Package Files Update


Revision History:

07/06/2015Added 64838
10/13/2014Added 62157

Linked Answer Records

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34904 Xilinx Configuration Solution Center N/A N/A
AR# 61598
Date 07/20/2017
Status Active
Type Design Advisory
Devices
  • Kintex UltraScale
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