UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61601

7 Series MIG DDR3 - Vivado 2014.2 - CLOCK_DEDICATED_ROUTE [Place 30-575] warning for IODELAYCTRL clk_ref

Description

Starting in MIG v2.1, a second MMCM is used to generate a 300 or 400 MHz reference clock when running above 1333 Mb/s (see Xilinx Answer 60687).  

If the ref_clk and IODELAYCTRL instantiation are not within the same bank, the following warning message will be given:

WARNING: [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.

                mpmc_inst/mc_axi_interconnect_inst/ddr3_cntrl_inst/u_ddr3_cntrl_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked to IOB_X1Y424

                mpmc_inst/mc_axi_interconnect_inst/ddr3_cntrl_inst/u_ddr3_cntrl_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i (MMCME2_ADV.CLKIN1) is locked to MMCME2_ADV_X1Y7

Resolution: A dedicated routing path between the two can be used if: (a) The clock-capable IO (CCIO) is placed on a CCIO capable site (b) The MMCM is placed in the same clock region as the CCIO pin. If the IOB is driving multiple MMCMs, all MMCMs must be placed in the same clock region, one clock region above or one clock region below the IOB. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays.



Solution

When sys_clk is used as source of IODELAYCTRL, a BACKBONE constraint is added to avoid potential problems. 

This message can be safely ignored. 

When an internal or another external clock source is used for IODELAYCTRL, a simple BUFG can be inserted between the clock input buffer and IODELAYCTRL MMCM.


Revision History:

08/06/2014 - Initial release.

AR# 61601
Date Created 07/23/2014
Last Updated 08/07/2014
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2014.2
IP
  • MIG 7 Series