We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61629

Vivado 2014.2 - LogiCORE UltraScale Archtecture Integrated block for Interlaken - How do I speed up simulation times?


The current simulation run time on ModelSim is over two hours.

Is there a way to speed up the simulation? 


Simulations involving the complex transceiver models can take long periods of time.  

To improve the simulation time we recommend use of Synopsys VCS or Cadence IES Simulators. 
If your simulation involves the Interlaken IP operating in a loopback scenario, an additional method to improve simulation time is to reduce the metaframe length by altering the value of the attributes, CTL_TX_MFRAMELEN_MINUS1 and CTL_RX_MFRAMELEN_MINUS1.

This should result in a shorter lane alignment phase at the expense of a large overhead. 

This change can only be made in simulation.

For a design to work in hardware the Interlaken specification recommendation must be followed. 


Linked Answer Records

Master Answer Records

AR# 61629
Date 10/13/2014
Status Active
Type General Article
  • UltraScale - Interlaken
Page Bookmarked