Chip Select 0 (CS0) does not go active when accessing anaddress in the range 0xE4000000 - 0xE5FFFFFF in the SRAM/NOR interface when thememory controller is configured to access a 64 MB memory device.
Work-around: You can implement either of the following workarounds:
Description: Aboard circuitry can be implemented as a work-around for ADDR 25 inversion andChip Select assertion.
Below are the steps:
Configure MIO0 as GPIO and drive constant 0.
This can be done as part of the NOR flash initialization.
Connect it to the chipenable input of the NOR flash device.
All Zynq devices withSRAM/NOR interface enabled for 64MB memory access.
There is currently no plan to fix this issue.
Please refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record.