The address bit 25 (A25) appears as 1 when accessing0xE2000000 - 0xE3FFFFFF and '0' when accessing 0xE4000000 - 0xE5FFFFFF in theSRAM/NOR interface when the memory controller is configured to access a 64 MBmemory device.
A board circuitry can be implemented as a workaround for ADDR 25 inversion and Chip Select assertion.
Below are the steps:
All Zynq devices with SRAM/NOR interface enabled for 64MB memory access.
There is currently no plan to fix this issue.
Please refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record.
Resolution: Implement the board level workaround