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AR# 6165

FPGA Express: Signal or port name expected as actual in association element (VSS-806)

Description

Keywords: FPGA Express, Foundation, actual, signal, VSS-806

Urgency: Standard

General Description:
Port map declarations similar to the example described below may produce the following error:

Signal or port name expected as actual in association element (VSS-806)

P1: C5LCR port map (P=>VALUE, CLK=>CLK, L=>LOAD, R=>START, CO=>DONE);

where VALUE is a constant defined as follows:

CONSTANT VALUE: STD_LOGIC_VECTOR (5 DOWNTO 0) := "010010";

Solution

The error may be produced due to a known issue whereby FPGA Express does not recognise
constants as acceptable connections to component ports. To resolve this problem see the
example provided.

Change the declaration of the constant to be a signal:

SIGNAL VALUE: STD_LOGIC_VECTOR (5 DOWNTO 0);

And after the "BEGIN" keyword assign the value intended to be the constant:

VALUE <= "010010";
AR# 6165
Date Created 04/13/1999
Last Updated 08/11/2003
Status Archive
Type General Article