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AR# 61655

v2014.2 - 'write_bd_tcl' command incorrectly creates an 'elseif' statement for checking if a design is empty or not.

Description

The 'write_bd_tcl' command incorrectly creates an 'elseif' statement for checking if a design is empty or not.
 
In the check to see if a design is empty or not there is an 'ne' not equal mathematical operator in the 'elseif' statement on line 66 instead of an 'eq' equal mathematical operator.

This causes issues when attempting to source two BD designs into one project.

Solution

The issue is with Line 66 of the tcl files where the 'elseif' is incorrect and an 'ne' operator is used instead of an 'eq'.

To resolve this issue, replace the incorrect code with the correct code below:
 
Incorrect Code:
Line 66

} elseif { ${cur_design} ne "" && ${cur_design} ne ${design_name} } {

 
Correct Code:
Line 66

} elseif { ${cur_design} ne "" && ${cur_design} eq ${design_name} } {

AR# 61655
Date Created 07/30/2014
Last Updated 07/31/2014
Status Active
Type General Article
Devices
  • FPGA Device Families
  • SoC
Tools
  • Vivado Design Suite