Version Found: v5.0 Rev1
Version Resolved: See (Xilinx Answer 58435)
MIG only supports behavioral simulations and does not support structural (i.e. gate-level) simulations of any kind.
However, when using the Out-Of-Context (OOC) flow, the <IP_name>_funcsim.v/.vhdl output products are still generated.
This can be misleading and will cause simulation failures if the <IP_name>_funcsim.v/.vhdl model is used.
Because only behavioral simulations are supported, the structural model should not be used.
This can be avoided by only running behavioral models or by manually compiling the MIG IP RTL when combining with structural models used by other IP.
08/05/2014 - Initial Release