We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61696

MIG UltraScale - the funcsim.v/.vhdl structural simulation model is not supported


Version Found: MIG UltraScale v5.0 Rev1
Version Resolved: See (Xilinx Answer 58435)

MIG only supports behavioral simulations and does not support structural (i.e. gate-level) simulations of any kind.

However, when using Out-Of-Context (OOC) flow the <IP_name>_funcsim.v/.vhdl output products are still generated.

This can be misleading and will cause simulation failures if the <IP_name>_funcsim.v/.vhdl model is used.


Since only behavioral simulations are supported the structural model should not be used.

This can be avoided by only running behavioral models or by manually compiling the MIG IP RTL when combining with structural models used by other IP.

Revision History

08/05/2014 - Initial Release

AR# 61696
Date 08/07/2014
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale
Page Bookmarked