I have a design where a Verilog module instantiates an instance of a VHDL file.
The instantiation includes several parameters passed to the instance.
When synthesizing, the following error is received:
Why is this happening?
The error is caused by a mixed language parameter/generic that specifies a negative bus range i.e. (-1 downto 0).
This happens when the parameter is defined as zero in the Verilog instantiation:
In the VHDL file, there are several bus ranges defined as:
This leads to the negative bus range and the error.
To avoid the error, the range should be 0 or positive.
When synthesizing the VHDL file as the top module that still specifies the negative range, there is no error, but the ports are removed: