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AR# 61720

Vivado Synthesis 2014.2 - Mixed language (VHDL Verilog) generic parameter passed causes Synth 8-26 error


I have a design where a Verilog module instantiates an instance of a VHDL file. 

The instantiation includes several parameters passed to the instance. 

When synthesizing, the following error is received:

[Synth 8-26] instantiation from Verilog of vhdl entity with complex port types not implemented ["/home/marcb/CASES/1018586/design/marc_psram_hdl_prj2/project_1/project_1.srcs/sources_1/imports/src/design_1_psram_ip_0_0.v":237]

Why is this happening?


The error is caused by a mixed language parameter/generic that specifies a negative bus range i.e. (-1 downto 0).

This happens when the parameter is defined as zero in the Verilog instantiation:

  psram_ip_v1_0 #(   




In the VHDL file, there are several bus ranges defined as:

std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0)


This leads to the negative bus range and the error.

To avoid the error, the range should be 0 or positive. 

When synthesizing the VHDL file as the top module that still specifies the negative range, there is no error, but the ports are removed:


WARNING: [Synth 8-506] null port 'S_AXI_ARUSER' ignored [/home/marcb/CASES/1018586/design/marc_psram_hdl_prj2/project_1/project_1.srcs/sources_1/imports/src/psram_ip_v1_0.vhd:144]

AR# 61720
Date 01/21/2015
Status Active
Type General Article
  • Vivado Design Suite - 2014.2