UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61790

7 Series MIG - DDR3 - app_rd_data_end stays high

Description

Version Found: MIG 7 Series v2.1
Version Resolved: See (Xilinx Answer 54025)

After toggling a number of times, app_rd_data_end may become stuck high as shown in the example design simulation below:

app_rd_data_end.PNG


Solution

With controllers using a 4:1 PHY to controller clock ratio, app_rd_data_end is always asserted high along with app_rd_data_valid.

Hence this signal is not needed for user logic and can be ignored. 

For 2:1 controllers, app_rd_data_end does toggle properly on the second word returned on app_rd_data.



Revision History

11/24/2014 - Initial Release


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 61790
Date Created 08/14/2014
Last Updated 01/09/2015
Status Active
Type Known Issues
IP
  • MIG 7 Series