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AR# 61805

MIG 7 Series - LPDDR2 calibration fails in Phase Detection when memory operating frequency is 200MHZ


Version Found: MIG 7 Series v2.1
Version Resolved: See (Xilinx Answer 54025)

MIG 7 Series LPDDR2 designs running at 200MHz might see hardware failures during the Phase Detection stage of calibration. 

This is due to phase difference between the memory reference clock and the DQS input strobe when they are at equal frequencies.

This makes edge detection unreliable.



If hardware failures are seen during the Phase Detection stage of calibration, increase the memory operating frequency to 220MHz or higher. 

This issue will be fixed in a future release of the IP.

Revision History

09/09/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 61805
Date 03/18/2015
Status Active
Type Known Issues
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