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AR# 61860

Vivado 2014.2 - Custom AXI slave example is corrupted when both AXI read and write channels are accessed on the same cycle


When AWVALID and ARVALID are asserted at the same time, the Vivado Create Custom IP AXI4 slave example will corrupt the BRAMs data, and potentially not respond correctly.

How do I resolve this issue?


The AXI4 Slave example uses a single-ported BRAM to represent a user's logic. 

Hence the independent AXI channels must be arbitrated together. 

The logic will not allow the other direction address to proceed during an active transaction. 

However this logic does not take into account the condition of both directions going active at the same time.

A fix is being investigated, and is currently planned for Vivado 2015.1.

AR# 61860
Date 08/28/2014
Status Active
Type General Article
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1
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