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AR# 61900

2014.2 - Vivado Logic Debug - Removing the debug core from the synthesized design, does not remove all the xdc constraints

Description

When removing a debug core from a design there might be some constraints that do not get completely removed.

This can result in critical warnings for these objects.
 
An example is below.

The following lines are not removed from the XDC file.

set_property C_CLK_INPUT_FREQ 300 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]

They result in the following Critical Warnings:

WARNING: [Vivado 12-750] There are no ChipScope debug cores in this design. [/proj/.../dut.xdc:11]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/proj/.../dut.xdc:11]
WARNING: [Vivado 12-750] There are no ChipScope debug cores in this design. [/proj/.../dut.xdc:12]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/proj/.../dut.xdc:12]
WARNING: [Vivado 12-750] There are no ChipScope debug cores in this design. [/proj/.../dut.xdc:13]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/proj//.../dut.xdc:13]
CRITICAL WARNING: [Vivado 12-1419] Debug core 'dbg_hub' was not found. [/proj/.../dut.xdc:14]

Solution

These critical warnings can be ignored.
AR# 61900
Date Created 09/02/2014
Last Updated 10/15/2014
Status Active
Type General Article
Devices
  • FPGA Device Families