UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61901

MIG UltraScale DDR3/DDR4 - memory model violations observed during simulation

Description

Version Found: MIG UltraScale v5.0 Rev1
Version Resolved: See (Xilinx Answer 58435)

The following violations might be observed when simulating MIG UltraScale DDR3/DDR4 designs:

DDR3:

# sim_tb_top.mem_model_x8.memModel[2].u_ddr3_x8: at time 0.0 ps ERROR: tIPW violation on CKE by 560.0 ps
# sim_tb_top.mem_model_x8.memModel[2].u_ddr3_x8.reset: at time 0.0 ps ERROR: CKE must be inactive when RST_N goes inactive.
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 2720347.0 ps ERROR: tIS violation on CKE by 170.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3044963.0 ps ERROR: tIS violation on BA 1 by 170.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3044963.0 ps ERROR: tIS violation on ADDR 3 by 170.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 4385315.0 ps ERROR: CAS Latency = 10 is illegal @tCK(avg) = 1308.937500
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 4385315.0 ps ERROR: CAS Latency = 10 is not valid when CAS Write Latency = 8

DDR4:

tWR/tRTP SPEC_VIOLATION tWR spec:12 loaded:10 tRTP spec:6250 loaded:6250 @4835815

Solution

These violations are safe to ignore as no calibration has been completed yet. 


Once calibration has completed these violations should be resolved.

Revision History
09/02/2014 - Initial Release

Linked Answer Records

Master Answer Records

AR# 61901
Date Created 09/02/2014
Last Updated 03/04/2015
Status Active
Type Known Issues
Devices
  • Virtex UltraScale
  • Kintex UltraScale
IP
  • MIG UltraScale